ISBN: 0818675454Fault tolerance has become a major concern in the design of VLSI systems. It is especially needed in finite state machines (FSMs) where a failure can have huge consequences on the whole circuit behavior. Several methods have been proposed in the last few years to implement such features in FSMs synthesized on standard cells. At the same time, considering circuit cost, performances and design efficiency, it has been shown that large controllers should rather be synthesized on a particular ROM-based architecture. The work presented here has consisted in studying, implementing and evaluating fault tolerance methods in FSMs in a ROM-based synthesis flow

ISBN: 0818663073This paper addresses the detection of permanent or transient faults in complex VLSI circuits, with a particular focus on faults leading to sequencing errors. On-line test devices are automatically generated by a specific synthesis tool (ASYL-SdF), avoiding design time overhead. Two approaches based on control-flow checking methods are available to the designer and it is shown that each of these approaches leads, in some cases, to the cheapest implementation. In particular, noticeable gains can be obtained compared with the classical approach based on duplication

ISBN: 0818681683We present here the first version of an automatic tool for the synthesis of dataparts with fault detection or tolerance characteristics. This work is to be combined with solutions already proposed for controllers, in order to provide a complete control-dominated synthesis flow allowing the synthesis of control/data architectures with fault detection or tolerance capabilities

ISBN: 0818635029Implementing single fault tolerant finite state machines (FSMs) in VLSI circuits might be done using triplication and voting (TMR). Alternatives are based on the use of an error correcting (SEC) code during the state assignment. Such architectures are studied and their characteristics are analyzed for a set of international and industrial FSM benchmarks. The results demonstrate that one of these architectures leads in some cases to implementation with less hardware overhead than TMR and should actually be considered for some types of circuits

ISBN: 4930813670This paper addresses the detection of permanent and transient faults in complex VLSI circuits, with a particular focus on faults leading to sequencing errors. Several Finite State Machine implementations using signature monitoring for control-flow checking are compared in terms of error detection latency, theoretical error coverage, experimental error coverage and area overheads. Advantages and drawbacks of each approach are presented