Alternative Standard Cell Placement Strategies for Single-Event Multiple-Transient Mitigation

Kiddie, Bradley T.; Robinson, William H.

doi:10.1109/isvlsi.2014.37

Cited by 15 publications

(9 citation statements)

References 14 publications

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“…Radiation robustness can also be obtained through reliability-aware logic and physical synthesis in semi-custom designs based on standard-cell methodology [18][19][20][21]. In other words, it is possible to harden a circuit by selectively using logic gates that minimize the SET generation or propagation in the most vulnerable nodes of a complex VLSI design.…”

Section: Radiation Hardening Based On Standard Cellsmentioning

confidence: 99%

“…It was shown that hardening techniques can be very effective when applied at standard cell based VLSI designs. During physical synthesis, hardening strategies can be explored in the cell placement to avoid charge sharing effects or to promote pulse quenching effects in electrically related combinational circuits [19][20][21]. Du et al [20] demonstrated that, as feature size shrinks, cell placement has a stronger impact on the soft error vulnerability of complex VLSI due to the multi-node collection process.…”

Section: Radiation Hardening Based On Standard Cellsmentioning

confidence: 99%

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Radiation hardening efficiency of gate sizing and transistor stacking based on standard cells

Aguiar

Wrobel

Guagliardo

et al. 2019

Microelectronics Reliability

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Soft error mitigation schemes inherently lead to penalties in terms of area usage, power consumption and/or performance metrics. This work provides a radiation hardening efficiency analysis of two possible selective node hardening based on standard cells: Gate Sizing and Transistor Stacking. The impact on the Single-Event Transient cross-section, layout area and leakage current is discussed. The results indicate that both techniques provide the same area overhead and high efficiency for low particle linear energy transfer. Further, although transistor stacking exhibits lower static power consumption, gate sizing still presents the best trade-off between area, performance and reliability.

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Section: Radiation Hardening Based On Standard Cellsmentioning

confidence: 99%

Section: Radiation Hardening Based On Standard Cellsmentioning

confidence: 99%

Radiation hardening efficiency of gate sizing and transistor stacking based on standard cells

Aguiar

Wrobel

Guagliardo

et al. 2019

Microelectronics Reliability

View full text Add to dashboard Cite

show abstract

“…4 (b), it provides very similar SET cross-section and increased threshold LET than the standalone OR2 gate. Table 1 Total area for the cell layout design used for the OR logic implementation, the charge collection area and the SET cross-section for a LET=78.23 MeV.cm 2 Now, considering the AND logic function implementation, the single cell AND2 is analyzed and compared with the NAND2 gate coupled with a minimum sized inverter in its output. Table 2 contains the total layout design area, total collection area and the SET cross-section for each circuit.…”

Section: Resultsmentioning

confidence: 99%

“…A Boolean function can be synthesized with a different combination of logic cells, implying a different number of transistors and layout design which directly impact the radiation robustness of the circuit. Recently, a great effort can be noticed from the research community in considering radiation hardening techniques early in the design flow of a VLSI circuit [1][2][3][4][5]. Once the highly vulnerable nodes are identified in a circuit, hardening approaches as transistor sizing or hardware redundancy can be added to improve the overall reliability of the circuit [6,7].…”

Section: Introductionmentioning

confidence: 99%

Analysis of the charge sharing effect in the SET sensitivity of bulk 45 nm standard cell layouts under heavy ions

Aguiar

Wrobel

Autran

et al. 2018

Microelectronics Reliability

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For nanometer technologies, SET is increasingly growing in importance in circuit design. Accordingly, different hardening techniques were developed to reduce the Soft-Error Rate. Considering selective node hardening technique based on standard cells, this work evaluates the SET response of logic gates from a Standard-Cell library under heavy ions. Overall, it is observed that the usage of NOR and NAND gates coupled with an output inverter provides reduced SET cross-section and increased threshold LET compared with the standalone OR gate and AND gate, respectively. With the results gathered in this work, circuit designers can implement reliability-aware synthesis algorithms with selective hardening more efficiently to tackle the threat of SET in combinational circuits.

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“…Several elements are important to address in this simulation and design process [Kiddie and Robinson 2014]. In order to modify the placement of a circuit intelligently and study how reliability varies with placement, hierarchical combinational circuits must be selected.…”

Section: Methodsmentioning

confidence: 99%

Single-Event Multiple-Transient Characterization and Mitigation via Alternative Standard Cell Placement Methods

Kiddie

Robinson

Limbrick

2015

ACM Trans. Des. Autom. Electron. Syst.

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As fabrication technology scales towards smaller transistor sizes and lower critical charge, single-event radiation effects are more likely to cause errant behavior in multiple, physically adjacent devices in modern integrated circuits (ICs), and with higher operating frequencies, this risk increasingly impacts design logic over memory as well. In order to increase future system reliability, circuit designers need greater awareness of multiple-transient charge-sharing effects during the early stages of their design flow with standard cell placement and routing. To measure the propagation and observability of multiple transients from single radiation events, this work uses several intra-pipeline combinational logic circuits at the 32nm technology node, investigates several different standard cell placements of each design, and analyzes those placements with a novel, physically realistic transient injection and simulation method. It is shown that (1) this simulation methodology, informed by experimental data, provides an increased realism over other works in traditional fault injection fields, (2) different placements of the same circuit where standard cells are grouped by logical hierarchy can result in different reliability behavior and benefits especially useful within the area of approximate computing, and (3) improved reliability through charge-sharing transient mitigation can be gained with no area penalty and minimal speed and power penalties by adjusting the placement of standard cells. ACM Reference Format: Bradley T. Kiddie, William H. Robinson, and Daniel B. Limbrick. 2015. Single-event multiple-transient characterization and mitigation via alternative standard cell placement methods.

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Alternative Standard Cell Placement Strategies for Single-Event Multiple-Transient Mitigation

Cited by 15 publications

References 14 publications

Radiation hardening efficiency of gate sizing and transistor stacking based on standard cells

Radiation hardening efficiency of gate sizing and transistor stacking based on standard cells

Analysis of the charge sharing effect in the SET sensitivity of bulk 45 nm standard cell layouts under heavy ions

Single-Event Multiple-Transient Characterization and Mitigation via Alternative Standard Cell Placement Methods

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Alternative Standard Cell Placement Strategies for Single-Event Multiple-Transient Mitigation

Cited by 15 publications

References 14 publications

Radiation hardening efficiency of gate sizing and transistor stacking based on standard cells

Radiation hardening efficiency of gate sizing and transistor stacking based on standard cells

Analysis of the charge sharing effect in the SET sensitivity of bulk 45 nm standard cell layouts under heavy ions

Single-Event Multiple-Transient Characterization and Mitigation via Alternative Standard Cell Placement Methods

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Product

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Analysis of the charge sharing effect in the SET sensitivity of bulk 45 nm standard cell layouts under heavy ions