Single-Event Multiple-Transient Characterization and Mitigation via Alternative Standard Cell Placement Methods

Abstract

As fabrication technology scales towards smaller transistor sizes and lower critical charge, single-event radiation effects are more likely to cause errant behavior in multiple, physically adjacent devices in modern integrated circuits (ICs), and with higher operating frequencies, this risk increasingly impacts design logic over memory as well. In order to increase future system reliability, circuit designers need greater awareness of multiple-transient charge-sharing effects during the early stages of their design flow with standard cell placement and routing. To measure the propagation and observability of multiple transients from single radiation events, this work uses several intra-pipeline combinational logic circuits at the 32nm technology node, investigates several different standard cell placements of each design, and analyzes those placements with a novel, physically realistic transient injection and simulation method. It is shown that (1) this simulation methodology, informed by experimental data, provides an increased realism over other works in traditional fault injection fields, (2) different placements of the same circuit where standard cells are grouped by logical hierarchy can result in different reliability behavior and benefits especially useful within the area of approximate computing, and (3) improved reliability through charge-sharing transient mitigation can be gained with no area penalty and minimal speed and power penalties by adjusting the placement of standard cells. ACM Reference Format: Bradley T. Kiddie, William H. Robinson, and Daniel B. Limbrick. 2015. Single-event multiple-transient characterization and mitigation via alternative standard cell placement methods.

Relative logic cell placement for mitigation of charge sharing-induced transients

“…EPP is calculated by the ratio of tests that resulted in errors observed at an output to the total number of tests run, and is a common method of reporting error susceptibility in logic designs (Miskov-Zivanov andMarculescu 2006, Limbrick et al 2011). Further detail on the SEMT modeling and characterization work flow are available in previous work (Kiddie et al 2015).…”

“…A handful of different methods have been proposed in recent years for SEMT modeling and characterization (Pagliarini et al 2011, Ebrahimi et al 2013, Kiddie et al 2015, Du and Chen 2016. Each of these methods starts with a fully placed circuit and analyzes placement in conjunction with netlist connectivity to quantify SEMT radiation sensitivity.…”

“…Section 3.1 provides the details of the SEMT characterization flow (Kiddie et al 2015), with added improvements to provide a more precise comparison of multiple design placements. Section 3.2 compares this SEMT modeling and characterization methodology with other methods available in the literature.…”