ALTIROC1, a 25 pico-second time resolution ASIC for the ATLAS High Granularity Timing Detector (HGTD)

Seguin-Moreau, N.; Conforti, S.; Dinaucourt, P.; Taille, C. De La; Martin-Chassard, Gisèle; Agapopoulou, C.; Makovec, N.; Serin, L.; Sacerdoti, S.; Dragone, A.; Marković, Bojan; Milke, C. D.; Ruckman, L.; Schwartzman, A.; Su, D.; Gong, D. T.; Ye, J.; Zhou, Wangming

doi:10.22323/1.370.0042

Cited by 8 publications

(7 citation statements)

References 1 publication

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“…Integrated readouts for LGAD sensors are under development e.g. for the ATLAS upgrade by OMEGA (ALTIROC [9]) and for the CMS upgrade by FNAL (ETROC [8,10]). The target time resolution for LGAD layers is 30 ps for a double layer.…”

Section: Existing Sensor Options and Readout Technologiesmentioning

confidence: 99%

STOPGAP -- a Time-of-Flight Extension for the Belle II TOP Barrel PID System as a Demonstrator for CMOS Fast Timing Sensors

Hartbrich¹,

Tamponi²,

Varner³

2022

Preprint

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The Belle II barrel region is instrumented with the Time of Propagation (TOP) particle identification system based on sixteen fused-silica bars arranged around the interaction point acting as Cherenkov radiator. Due to the mechanical design of the TOP system these quartz bars do not overlap, but leave a gap of around 2 cm between them. This leads to around 6 % of all tracks in the nominal TOP acceptance region to escape without traversing any of the quartz bars and thus not giving any usable particle identification information from the TOP system and an additional 3 % of tracks being degraded due to edge effects. We propose a possible solution to remedy these gaps in the TOP acceptance in the form of a Supplemental TOP GAP instrumentation (STOPGAP) that covers the dead area between adjacent quartz bars with fast silicon detectors to directly measure the time-offlight of traversing particles for particle identification purposes. Modern, fast timing silicon sensors and readouts can offer sufficient time resolution for the task at hand, so that STOPGAP modules could be built compact enough to fit into the limited space available in the area of interest between the Belle II central drift chamber (CDC) and the TOP system.In this article, we present a simulation study demonstrating the feasibility of a silicon time-offlight system based on its reconstruction performance in Υ(4S) → B B events simulated using the Belle II simulation and reconstruction software. We discuss the performance requirements for possible sensor technologies and demonstrate that such a project could be realised with novel, fast monolithic CMOS sensors that are expected to reach MIP timing resolutions of down to 50 ps. Additionally, we discuss the use of fast timing layers at lower radii for track triggering as well as particle identification at low momenta <1 GeV/c.

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Section: Existing Sensor Options and Readout Technologiesmentioning

confidence: 99%

STOPGAP -- a Time-of-Flight Extension for the Belle II TOP Barrel PID System as a Demonstrator for CMOS Fast Timing Sensors

Hartbrich¹,

Tamponi²,

Varner³

2022

Preprint

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“…During the research and development of the LGAD readout, some prototype ASICs have been designed and tested, such as ALTIROC [11,12] and ETROC [13,14], and the research is going on. During the development of both ALTIROC and ETROC, their first versions aim to study the performance of the analog front-end, without on chip TDC.…”

Section: Jinst 17 T09004mentioning

confidence: 99%

“…Usually there are two ways to achieve this requirement, using common gate structure (shown in figure 2(a)), e.g. like NINO ASIC [18], or common source structure with a feedback resistor (shown in figure 2(b)), like ALTIROC [11,12] and ETROC [13,14]. The former way, common gate structure, is able to keep a low input impedance in a wide bandwidth, so it is suitable to match the impedance of transmission line.…”

Section: Pre-amplifiermentioning

confidence: 99%

Design of a prototype analog front-end ASIC for the LGAD readout

et al. 2022

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Low-gain avalanche detector (LGAD) is being researched and designed in ATLAS and CMS experiments aiming to distinguish collisions that are close in both space and time to meet the challenge of pileup in HL-LHC, through its high resolution in position and time measurement. Considering the high spatial density of the detector channels, the area and power consumption per each channel are quite limited, so a front-end ASIC, instead of discrete-component electronics, is expected to collect and process the signal output by the LGAD. The processed signal is a digital pulse containing the precise information of time of arrival (TOA) and time over threshold (TOT). A prototype analog front-end ASIC for LGAD readout based on 180 nm CMOS technology with low power consumption, called LATIC0, has been designed and tested. As the first prototype, this ASIC aims to study the performance of the analog front-end for the further work. And the test results indicate that a time precision better than 20 ps-rms is achieved (at 10 fC injected charge with 6 pF capacitance), and the curves of TOA and TOT versus charge concord well with expectations.

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“…In the S-curve measurement for ETROC threshold calibration, the discriminator threshold is described as charge (unit: fC) [15,16]. At least two runs of the S-curve measurements are needed to derive the preamplifier gain (unit: mV/fC) and set a threshold.…”

Section: S-curve Measurementmentioning

confidence: 99%

In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip

Sun¹,

Gong²,

Edwards³

et al. 2021

J. Inst.

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We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC) needs to be calibrated regularly to mitigate the circuit baseline change. Traditional methods need a lot of communication through a slow control system hence are time-consuming. This paper describes an in-pixel automatic scheme with improvements in operating time and usability. In this scheme, a sample-accumulation circuit is used to measure the average discriminator output. A binary successive approximation and linear combination scan are applied to find the equivalent baseline. The actual calibration procedure has been first implemented in FPGA firmware and tested with the ETROC front-end prototype chip (ETROC0). The calibration circuit has been implemented with Triple Modular Redundancy (TMR) and verified with Single Event Effects (SEEs) simulation. A complete calibration process lasts 35 ms with a 40 MHz clock. In the worst case, the dynamic and static power consumption are estimated to be 300 μW and 10.4 μW, respectively. The circuit design, implemented in a 65 CMOS technology, will be integrated into ETROC2, the next iteration of the ETROC with a 16 × 16 pixel matrix.

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ALTIROC1, a 25 pico-second time resolution ASIC for the ATLAS High Granularity Timing Detector (HGTD)

Cited by 8 publications

References 1 publication

STOPGAP -- a Time-of-Flight Extension for the Belle II TOP Barrel PID System as a Demonstrator for CMOS Fast Timing Sensors

STOPGAP -- a Time-of-Flight Extension for the Belle II TOP Barrel PID System as a Demonstrator for CMOS Fast Timing Sensors

Design of a prototype analog front-end ASIC for the LGAD readout

In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip

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