ALU design using reconfigurable CMOS logic

Srivastava, Ashok; Srinivasan, C.

doi:10.1109/mwscas.2002.1186949

Cited by 14 publications

(5 citation statements)

References 5 publications

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“…To avoid the mutual restriction between coupling capacitors and customized ratio of the transistor with MIFGs in this work, for any transistor with MIFGs, we have used another structure shown in Figure 2(c) to achieve coupling capacitors, which are implemented by standard n-diffusion capacitors. This design style of MIFG MOSFETs is fully compatible with the fabrication flow of standard CMOS and already proposed, fabricated, and tested in the work of Shibata and Ohmi (1992), Srivastava and Srinivasan (2002), Srivastava and Venkata (2003), and Subramanian (2005). The essence of this structure is that the coupling capacitors are designed in the area beside MIFG transistors but not over the floating gate.…”

Section: Multiple-input Floating Gate Mosfetmentioning

confidence: 88%

“…In analog IC design, normal MOSFETs used in the input stage only map injective functions to the output. To overcome this restriction, MIFG MOSFET is introduced to increase both the inputs for a single transistor and the reconfigurable output (Shibata and Ohmi 1992;Srivastava and Srinivasan 2002;Ramirez-Angulo et al 2004;Subramanian 2005). The MIFG MOSFET has two gate layers.…”

Section: Multiple-input Floating Gate Mosfetmentioning

confidence: 99%

See 1 more Smart Citation

Long Short-Term Memory Network Design for Analog Computing

Zhao

Srivastava

Peng

et al. 2019

J. Emerg. Technol. Comput. Syst.

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We present an analog-integrated circuit implementation of long short-term memory network, which is compatible with digital CMOS technology. We have used multiple-input floating gate MOSFETs as both the front-end to obtain converted analog signals and the differential pairs in proposed analog multipliers. Analog crossbar is built by the analog multiplier processing matrix and bitwise multiplications. We have shown that using current signals as internal transmission signals can largely reduce computation delay, compared to the digital implementation. We also have introduced analog blocks to work as activation functions for the algorithm. In the back-end of our design, we have used current comparators to achieve the output to be readable to external digital systems. We have designed the LSTM network with the matrix size of 16 × 16 in TSMC 180nm CMOS technology. The post-layout simulations show that the latency of one computing cycle is 1.19ns without memory, and power dissipation of the single analog LSTM computing core with 2 kilobytes SRAM at 200MHz is 460.3mW. The overhead of power dissipation due to SRAM access is 8.3%, in which the computing of each LSTM layer requires one computing cycle. The energy efficiency is 0.95TOP/s/W.

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Section: Multiple-input Floating Gate Mosfetmentioning

confidence: 88%

Section: Multiple-input Floating Gate Mosfetmentioning

confidence: 99%

Long Short-Term Memory Network Design for Analog Computing

Zhao

Srivastava

Peng

et al. 2019

J. Emerg. Technol. Comput. Syst.

View full text Add to dashboard Cite

show abstract

“…9, 10 below shows Novel NOR gate and its symbol, Fig. 11 shows NOVEL NOR gate input verses output waveforms [11][12][13], Table 7 shows NOR gate truth table and Table 8 shows Traditional NOR gate verses Novel NOR gate Power, Delay and PDP. Table 7: NOR GATE truth table A B VOUT 0 0 1 0 1 0 1 0 0 1 1 0 3.961x10 -14 Fig .…”

Section: Figurementioning

confidence: 99%

Design of ALU System Using Novel PMOS and NMOS for Low Power and High Speed Applications

Babu¹,

Ravindra²,

Kishore³

2018

IJET

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This paper tailors 8 bit ALU for high speed and low power applications. In this design a novel PMOS and NMOS are used in place of conventional PMOS and NMOS. The main disadvantage of conventional PMOS and NMOS is low speed. With the technique of forward body biasing a novel PMOS and NMOS are derived and speed is improved. For each sub module of ALU power delay product percentage is calculated. Percentage improvement in power delay product of Novel ALU is shown in table 27.

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“…Harrison et al [7] propose an analog floating memory element for on-chip storage of bias voltages. A floating gate technology has been used to eliminate off-chip biasing voltages in the existing systems by providing these voltages on-chip, with arrays of programmable floating-gate voltages.…”

Section: Related Workmentioning

confidence: 99%

Design and Implementation of 4-Bit Arithmetic and Logic Unit Chip with the Constraint of Power Consumption

Yadav¹,

Kumar²,

Gupta³

2014

IOSRJECE

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By increasing the demand of enhancing the ability of processors to handle the more complex and challenging processors has resulted in the integration of a number of processor cores into one chip. Still the load of on the processor is not less in generic system. An Arithmetic Logic Unit (ALU) is the heart of all microprocessors. It is a combinational logic unit that performs its logical or arithmetic operations. ALU is getting smaller and more complex nowadays to enable the development of a more powerful but smaller computer. In this proposed paper a 4 bit ALU chip has been design to the benefits of all the computations are done in parallel and available simultaneously, so no clock resources are wasted. The MUX is then simply used to select the required output.

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ALU design using reconfigurable CMOS logic

Cited by 14 publications

References 5 publications

Long Short-Term Memory Network Design for Analog Computing

Long Short-Term Memory Network Design for Analog Computing

Design of ALU System Using Novel PMOS and NMOS for Low Power and High Speed Applications

Design and Implementation of 4-Bit Arithmetic and Logic Unit Chip with the Constraint of Power Consumption

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