Ambipolar silicon nanowire FETs with stenciled-deposited metal gate

Sacchetto, Davide; Savu, Veronica; Micheli, Giovanni De; Brugger, Jürgen; Leblebici, Yusuf

doi:10.1016/j.mee.2010.12.117

Cited by 12 publications

(8 citation statements)

References 10 publications

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“…Moreover, polycrystalline SiNWs SB FETs can give a hysteretic transfer characteristic (Fig. 20) very similar to the one reported for crystilline SiNW SB FETs fabricated with a low thermal budget process [39]. As is shown in Fig.…”

Section: B Current-controlled Four-terminal Memristive Devicessupporting

confidence: 76%

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Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

2012

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| Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic, and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devices, whose practical realization has been demonstrated within a broad range of different technologies. For electron devices, the memristive functionality can be generally attributed to a material state modification, whose dynamics can be engineered to target a specific application. In this review paper, we show that trap charging dynamics can explain some of the memristive effects previously reported for Schottky-barrier field-effect Si nanowire transistors (SB SiNW FETs). Moreover, the SB SiNW FETs do show additional memristive functionality due to trap charging at the metal/ semiconductor surface. The combination of these two memristive effects into multiterminal metal-oxide-semiconductor field-effect transistor (MOSFET) devices gives rise to new opportunities for both memory and logic applications as well as new sensors based on the physical mechanism that originate memristance. In the special case of four-terminal memristive Si nanowire devices, which are presented for the first time in this paper, enhanced functionality is demonstrated. Finally, the multiterminal memristive devices presented here have the potential of a very high integration density, and they are suitable for hybrid complementary metal-oxide-semiconductor (CMOS) cofabrication with a CMOS-compatible process.

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Section: B Current-controlled Four-terminal Memristive Devicessupporting

confidence: 76%

“…More details about the process flow can be found in [9], [36], and [39] for crystalline-Si (c-Si), polycrystalline-Si (poly-Si), and amorphous-Si (-Si) nanowire channels. All the techniques yield nanowires with a subphotolithographic thickness.…”

Section: Si Nanowire Memristive Device Fabrication Methodsmentioning

confidence: 99%

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

2012

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“…Moreover, polycrystalline SiNWs SB FETs can give an hysteretic transfer characteristic (Fig. 20) very similar to the one reported for crystalline SiNW SB FETs fabricated with a low thermal budget process [56]. As it is shown in Fig.…”

Section: Current-controlled 4-t Memristive Devicessupporting

confidence: 76%

“…In Fig. 42b, forward and reverse threshold voltages for currents between 100 fA and 500 fA show a linear increase with current (adapted from [72]). A shows constant E a ≈ 450 ± 5meV.…”

Section: Current Sensingmentioning

confidence: 99%

Memory Effects in Multi-terminal Solid State Devices and Their Applications

Sacchetto¹,

Gaillardon²,

Leblebici³

et al. 2014

Memristor Networks

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“…In a previous work, the authors envisaged stencil lithography [6] as a key enabler for gate patterning on 3D structures, such as vertically-stacked Si NW transistors [4]. In this work, nanostencil lithography is used to deposit the Al mask used to pattern sub-lm GAA polysilicon gates deposited with LPCVD as alternative solution for patterning nanoscaled features having high aspect ratio, which is a non trivial issue in photo-resist lithography.…”

Section: Introductionmentioning

confidence: 99%

Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-μm gates patterned by nanostencil lithography

Sacchetto

Xie

Savu

et al. 2012

Microelectronic Engineering

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a b s t r a c tWe report on the top-down fabrication of vertically-stacked polysilicon nanowire (NW) gate-all-around (GAA) field-effect-transistors (FET) by means of Inductively Coupled Plasma (ICP) etching and nanostencil lithography. The nanostencil is used to form sub-lm GAA gates over polysilicon NW array channels with high aspect ratio, considerably simplifying the lithographic steps above regions with deep 3D topography and non-planar surface features. This process lead to fabrication yields larger than 70% and authors envisage even larger yields of P 85% with optimized mask design. Electrical measurements confirm the results obtained from similar devices fabricated with a standard lithography method while achieving higher density, larger reproducibility and yield, maintaining the performance improvement related with scaling.

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Ambipolar silicon nanowire FETs with stenciled-deposited metal gate

Cited by 12 publications

References 10 publications

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

Memory Effects in Multi-terminal Solid State Devices and Their Applications

Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-μm gates patterned by nanostencil lithography

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