AMODA: a flexible framework for automatic migration of analog macro designs using optimization techniques

Wu, P.; Mack, R.J.; Massara, R.E.; Bensouiah, D.A.; Kemp, A.

doi:10.1109/mwscas.2000.952920

Cited by 3 publications

(2 citation statements)

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“…Last but not least, the associated optimization procedure generates new designs automatically, which will not only meet design goals but also achieve better overall performance. The works on this approach include AMODA [6], ASTRX/OBLX [18], STAR [19], Anaconda [5], as well as commercial synthesis tools [27], [28]. Our proposed method falls into this category.…”

Section: ) Analytical Equation/linearized Equivalent Model-based Appmentioning

confidence: 99%

“…The key hurdle that prevents the transition from cell level to system level is that system-level design is associated with a large number of design variables, resulting in an incontrollable search space. 2) The optimization algorithms utilized by most approaches have either initial points dependency problem, like gradient-based algorithms [6], or slow convergence problem, such as genetic algorithms [20], [21], geometric programming [22], [23], and simulated annealing [19]. 3) Most existing process migration approaches are failing to consider circuit reliability and robustness.…”

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confidence: 99%

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Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework

Qian

Zhou

et al. 2015

IEEE Trans. VLSI Syst.

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Optimization-simulation loop-based method is popular and efficient in design migration/reuse automation. However, it is only restricted to be used in block-level due to the complexity of current mixed-signal system. This paper presents a hierarchical methodology for efficiently migrating mixed-signal circuit design from one technology node to another, while keeping the same circuit and layout topologies. It utilizes two stages of optimization processes to automatically resize and refine device dimensions in target technology. In the first stage, to avoid the costly simulation time without scarifying systematical functionality, only one block is represented in transistor level (TL), while other blocks are replaced with behavioral models. The multistart global optimization technique is applied to resize the TL block in systematic connection. This stage provides a good initial point for next system-level refinement. Moreover, for obtaining a process and parasitic closure solution, both parasitic and process variation effects are explored and used to constrain the schematic migration. A representative mixed-signal system, charge-pump phase-locked loop, is used to validate the proposed methodology. The experimental results show that the proposed methodology efficiently generates quality designs in target technology with much less simulation iterations, when comparing with recent available approaches. IndexTerms-Design reuse, optimization method, phase-locked loop (PLL), technology migration.

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Section: ) Analytical Equation/linearized Equivalent Model-based Appmentioning

confidence: 99%

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confidence: 99%

Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework

Qian

Zhou

et al. 2015

IEEE Trans. VLSI Syst.

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A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes

Nalam

Bhargava

Ringgenberg

et al. 2009

2009 IEEE International Conference on Computer Design

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-A designer's intent and knowledge about the critical issues and trade-offs underlying a custom circuit design are implicit in the simulations she sets up for design creation and verification. However, this knowledge is tightly conjoined with technology-specific features and decoupled from the final schematic in traditional design flows. As a result, this knowledge is easily lost when the technology specifics change. This paper presents a Technology Agnostic Simulation Environment (TASE), which is a tool that uses simulation templates to capture the designer's knowledge and separate it from the technologyspecific components of a simulation. TASE also allows the designer to form groups of related simulations and port them as a unit to a new technology. This allows an actual design schematic to remain tied to the analyses that illuminate the underlying trade-offs and design issues, unlike the case where schematics are ported alone. Giving the designer immediate access to the trade-offs, which are likely to change in new technologies, accelerates the re-design that often must accompany porting of complicated custom circuits. We demonstrate the usefulness of TASE by investigating Read and Write noise margins for a 6T SRAM in predictive technologies down to 16 nm. I. INTRODUCTIONThe rapid creation of new technologies according to Moore's Law has made cross-technology porting an important part of circuit design. An ideal method for porting custom circuits would reuse an existing design in a new technology while also re-optimizing or restructuring the design to best take advantage of that process's features. For complicated blocks that defy complete automation, the best way to do this would expose the tradeoffs and knowledge that underlie the original design in full view of the designer in the new technology. Existing methods for porting offer imperfect solutions. Classic ASIC flows approach porting by largely decoupling the design (e.g. HDL) from a specific technology. The foundry typically provides the process dependent part of the design flow (standard cell library), allowing for relatively easy porting. Custom circuits, on the other hand, require more careful designer intervention for process porting. A large number of tools exist for direct porting of custom layout (e.g. [1]), but these do not carry any useful design information to help a custom designer. To access design information, designers can use built-in SPICE features (.alter, .param, .lib) that allow single netlists to support multiple processes, but these features become unwieldy for complex designs or when reusing netlists for different simulations. Many designers employ their own scripts for porting designs and simulations, but these tend to be ad hoc, proprietary, or generally unavailable to the community.A large variety of optimization tools for analog circuits have been proposed, and some of these aid with process porting (e.g. [2]). The tool in [3] ports analog schematics and layout by identifying known sub-blocks (e.g. current mirror) and...

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Metodologia para a otimização do rendimento e desempenho dos circuitos analógicos usando programação geométrica.

Noval¹,

Johanny²

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This work proposed a Design Methodology for Manufacturing (DFM) using Geometric Programming (GP) and Newton-like methods to solve non-linear optimization problems, which define and aid the design of analog circuits. Afterwards, this methodology is applied and validated through the design of a voltage reference circuit.Over the last years, the tendency of the increasing on the transistor density predicted by the Moore Law has turned the circuit design problem dimensionally more complex. Additionally, a higher transistor density implies shrinkage on the feature dimensions of the process making it more sensitive to the process variations and environmental conditions. The differences between the designed circuit and the tested one give an evidence of yield losses, which are attributed in a great proportion to the design process. Due to the high responsibility of the designer on this problem, the analog design must be focused on new approaches that jointly manage performance and yield.In first place, the proposed methodology obtain a initial point with a suitable set of performance specifications, which will be used to analyze the impact of the mismatch and process variation over the design specifications. Once the statistical and deterministic behavior of the circuit was characterized, a new yield improvement strategy is implemented using Geometric Programming. Attempting to obtain a design with a set of high performance specifications directly involves the circuit yield, because an optimal performance set obtained by the traditional framework of GP does not assure the obtaining of a marketable and competitive design. So, this works establish a design method that combine the advantage of obtaining global optimum in Geometric Programming with a new mismatch and worst-case analysis that enabled a reduction in their computation time and maintain the initial nominal performance values. Using the design methodology for manufacturing proposed in this work, a voltage reference design with 37% better yield than one obtained with a typical design strategy without any significant penalty on their performance specs was achieved.

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AMODA: a flexible framework for automatic migration of analog macro designs using optimization techniques

Cited by 3 publications

References 5 publications

Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework

Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework

A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes

Metodologia para a otimização do rendimento e desempenho dos circuitos analógicos usando programação geométrica.

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