No abstract

No abstract

The process variations are unavoidable in today's VLSI circuits due to the continuing scaled IC technologies, therefore, the likely behaviors of VLSI circuits with process variations may fail to meet the performance specifications. This paper addresses an efficient method to evaluate the performance bounds of VLSI circuits with process variations in time domain. The described approach proceeds by solving a Nonlinear Programming (NLP) problem to find the upper and lower bounds of the interested outputs, either a node voltage or a branch current, constrained by linearlized equations, circuit equations and parameter variations. The preliminary result shows the performance bounds from the proposed method are sufficiently tight comparing with the bounds obtained from intensive Monte Carlo samplings in SPICE.

Optimization-simulation loop-based method is popular and efficient in design migration/reuse automation. However, it is only restricted to be used in block-level due to the complexity of current mixed-signal system. This paper presents a hierarchical methodology for efficiently migrating mixed-signal circuit design from one technology node to another, while keeping the same circuit and layout topologies. It utilizes two stages of optimization processes to automatically resize and refine device dimensions in target technology. In the first stage, to avoid the costly simulation time without scarifying systematical functionality, only one block is represented in transistor level (TL), while other blocks are replaced with behavioral models. The multistart global optimization technique is applied to resize the TL block in systematic connection. This stage provides a good initial point for next system-level refinement. Moreover, for obtaining a process and parasitic closure solution, both parasitic and process variation effects are explored and used to constrain the schematic migration. A representative mixed-signal system, charge-pump phase-locked loop, is used to validate the proposed methodology. The experimental results show that the proposed methodology efficiently generates quality designs in target technology with much less simulation iterations, when comparing with recent available approaches. IndexTerms-Design reuse, optimization method, phase-locked loop (PLL), technology migration.

No abstract