No abstract

The process variations are unavoidable in today's VLSI circuits due to the continuing scaled IC technologies, therefore, the likely behaviors of VLSI circuits with process variations may fail to meet the performance specifications. This paper addresses an efficient method to evaluate the performance bounds of VLSI circuits with process variations in time domain. The described approach proceeds by solving a Nonlinear Programming (NLP) problem to find the upper and lower bounds of the interested outputs, either a node voltage or a branch current, constrained by linearlized equations, circuit equations and parameter variations. The preliminary result shows the performance bounds from the proposed method are sufficiently tight comparing with the bounds obtained from intensive Monte Carlo samplings in SPICE.

Continuous scaling in CMOS fabrication process makes integrated circuits more vulnerable to process variations. The impact on circuit performance caused by process variations in CMOS circuit is usually analyzed by Monte Carlo method with a large number of simulation runs. This paper proposes a novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations. The accuracy of the small signal model has been verified with CMOS circuit. The proposed approach has been demonstrated by a CMOS two-stage operational transconductance amplifier (OTA). To achieve an accurate estimate, the modified small signal model which consider more parasitic capacitors in CMOS transistor, has been applied in the proposed approach. By applying the proposed approach based on optimization method, the upper and lower bounds of magnitude and phase, can be evaluated accurately in much less computation time compared to Monte Carlo simulations. All experimental results are carried out using a standard 0.35-µm CMOS process technology.

The continued scaling of the minimum feature size of contemporary chips has made circuit performance increasingly susceptible to the process variations. Many approaches have been proposed to estimate the circuit performance bounds with respect to process or circuit parameter variations in the recent years. The Monte Carlo method is the most popular one among them. However, this method usually produces underestimated results and needs a large number of simulation runs to achieve an accurate estimation. The approach based on Kharitonov's method has been recently proposed. This method requires all coefficient variations in the system transfer function to be independent from each other. Unfortunately, most real circuits do not satisfy this constraint. Therefore, it tends to overestimate the performance bounds in real application due to the parameter-independent requirement. This short paper proposes an optimization approach on a transfer function of a linear circuit to evaluate the performance bounds under process variations. The magnitude and phase bounds of a linear system can be calculated by the proposed method at each frequency point. Furthermore, the parameter-independent requirement in Kharitonov's method is resolved by the proposed method. The proposed method has been applied to a CMOS two-stage amplifier. The experimental result shows that it evaluates the magnitude and phase bounds of a linear system accurately in much less computation time as compared with the Monte Carlo method. All experimental results were carried out using a standard 0.35-µm CMOS process technology.

SAT problem has been an active research subject and many impressive SAT solvers have been proposed. Most of algorithms used in modern SAT solvers are based on tree structured searching strategy, combining with heuristic approaches to reduce the search space. In contrast to most existing solvers, we treat SAT problem as a logical optimization issue which can be solved by a logic minimizer. In this paper, we propose a Folding Strategy (FS) based on the Shannon's expansion theorem such that in every step, one variable is deducted and the size of search space is shrunk. The new method will find the solution after Karnaugh Map (K-Map) is folded no more than n (number of variables) times because search space is decreased by half in each folding step.