Amorphous-InGaZnO4 Thin-Film Transistors with Damage-Free Back Channel Wet-Etch Process

Ryu, Sang Hyun; Park, Young Chul; Mativenga, Mallory; Kang, Da Hyun; Jang, Jin

doi:10.1149/2.004202ssl

Cited by 88 publications

(65 citation statements)

References 16 publications

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“…After patterning the a-IGZO layer to form an active island by wet etching with an indium tin oxide (ITO) etchant, a 150 nm thick Mo layer was deposited and patterned by a wet etch process to form the source and drain electrodes. To minimize damage to the back channel of the active a-IGZO, a hydrogen peroxide (H 2 O 2 ) based etchant was used for the patterning of the source and drain electrodes [12]. 0741-3106 © 2014 IEEE.…”

Section: Methodsmentioning

confidence: 99%

Removal of Negative-Bias-Illumination-Stress Instability in Amorphous-InGaZnO Thin-Film Transistors by Top-Gate Offset Structure

Lee

Mativenga

Jang

2014

IEEE Electron Device Lett.

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A highly stable, dual-gate (DG) amorphous, indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) with an offset top-gate (TG) is reported. Given that both gates are opaque and electrically tied together, the TG functions as a lightshield and drain-current (I DS ) enhancer as synchronized gatevoltage (V GS ) sweep induces bulk-accumulation (BA) at positive voltages. It is demonstrated here that regardless of the offsets between the TG and source/drain electrode, this BA a-IGZO TFT is immune to negative bias and light-illumination stress (NBIS) when the TG covers at least 50% of the channel region. Therefore, high performance BA a-IGZO TFTs that are also immune to NBIS can be designed without introducing additional parasitic capacitance that occurs when the TG overlaps the source and/or drain electrode(s).Index Terms-a-IGZO, bulk accumulation, dual gate, negative bias illumination stress (NBIS), thin film transistor (TFT).

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Section: Methodsmentioning

confidence: 99%

Removal of Negative-Bias-Illumination-Stress Instability in Amorphous-InGaZnO Thin-Film Transistors by Top-Gate Offset Structure

Lee

Mativenga

Jang

2014

IEEE Electron Device Lett.

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“…To minimize damage to the back channel of the active a-IGZO, a hydrogen peroxide (H 2 O 2 ) based etchant was used for the patterning of the source and drain electrodes. 16 A 300 nm thick SiO 2 layer was deposited as the TG insulator by PECVD at 300 • C. The TG insulator also plays a role as passivation of the a-IGZO layer and protect from exposure to air. Annealing was carried out at 250 • C in vacuum for 4 hours to achieve a reproducible unstressed state.…”

Section: -3mentioning

confidence: 99%

Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

2015

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We investigated the effects of top gate voltage (VTG) and temperature (in the range of 25 to 70 oC) on dual-gate (DG) back-channel-etched (BCE) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) characteristics. The increment of VTG from -20V to +20V, decreases the threshold voltage (VTH) from 19.6V to 3.8V and increases the electron density to 8.8 x 1018cm−3. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on VTG. At VTG of 20V, the mobility decreases from 19.1 to 15.4 cm2/V ⋅ s with increasing temperature, showing a metallic conduction. On the other hand, at VTG of - 20V, the mobility increases from 6.4 to 7.5cm2/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.

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“…The wet-etching can avoid such plasma bombardment induced damage; however, the oxide semiconductor like a-IGZO is very susceptible to a strong acidic or alkaline etchant [4]. Furthermore, some conductive metal oxides were generated during the wet-etching process, which reside on the back channel and are difficult to remove [5], [6], degenerating the device performance severely.…”

Section: Introductionmentioning

confidence: 99%

P-15: AZO Etch Buffer Layer based Back-Channel-Etch a-IGZO TFT Technology

Song

Wang

Xiao

et al. 2016

SID Symposium Digest of Technical Papers

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Amorphous-InGaZnO4 Thin-Film Transistors with Damage-Free Back Channel Wet-Etch Process

Cited by 88 publications

References 16 publications

Removal of Negative-Bias-Illumination-Stress Instability in Amorphous-InGaZnO Thin-Film Transistors by Top-Gate Offset Structure

Removal of Negative-Bias-Illumination-Stress Instability in Amorphous-InGaZnO Thin-Film Transistors by Top-Gate Offset Structure

Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

P-15: AZO Etch Buffer Layer based Back-Channel-Etch a-IGZO TFT Technology

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