AMULET3: a 100 MIPS asynchronous embedded processor

Furber, Steve; Edwards, Doug; Garside, Jim

doi:10.1109/iccd.2000.878304

Cited by 51 publications

(31 citation statements)

References 10 publications

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“…The Amulet processor core developed at Manchester, which implements the ARM instruction set, is in its third generation and is commercially viable [3]. As Ronen et al mention in [2], the worsening interconnect and clock distribution problem, as well as the burden of high clock power cost can be potentially solved by employing a global asynchronous design as a possible solution.…”

Section: Related Workmentioning

confidence: 99%

Power efficiency of voltage scaling in multiple clock, multiple voltage cores

Iyer

Marculescu

2002

Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '02

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Section: Related Workmentioning

confidence: 99%

Power efficiency of voltage scaling in multiple clock, multiple voltage cores

Iyer

Marculescu

2002

Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '02

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“…1 Researchers have also shown that, because of the absence of a clock and natural support of idle mode, such designs might consume less power than synchronous designs. 2,3 Finally, asynchronous designs incur low EMI and noise, thanks to their even time distribution of switching activities. 4 (See the "Practical asynchronous circuits and tools" sidebar for another perspective on asynchronous design from a leading expert in the field.…”

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confidence: 99%

Design of asynchronous circuits using synchronous CAD tools

Kondratyev

Lwin

2002

IEEE Des. Test. Comput.

117

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Alex KondratyevCadence Berkeley Laboratories Kelvin LwinReshape Inc.ods for control synthesis and synchronous methods for data path design. Communication among these circuit elements rests on timing assumptions and delay-matching mechanisms. The latter makes verifying such circuits difficult.To further complicate the situation, a lack of commercial CAD support for asynchronous synthesis sometimes forces designers to use inhouse specification languages and design tools. 2,3 This chronic deficiency is a major roadblock to wider acceptance of asynchronous methodologies.Low EMI and noise coefficients are the only "free" advantages of asynchronous circuits. Special DAC Section 108 IEEE Design & Test of Computers Alain J. Martin, California Institute of TechnologyAfter looking like a pipe dream for many years, asynchronous technology is becoming a viable-and perhaps unavoidable-alternative to clocked design for large VLSI systems. Asynchronous technology rests on local communications among concurrent units. Handshake protocols implement communication and synchronization among those units. There is no concept of global time-no clocks-and no assumptions about the duration of an action or communication. Asynchronous circuits have several advantages:I They avoid all issues related to distributing a clock signal reliably and efficiently across a large chip.I Because they can be largely insensitive to delay variations, asynchronous circuits can tolerate large variations in a design's physical parameters, which are difficult to control in deep-submicron technology.I They offer, to the designer of low-power systems, automatic and perfect shut-off of idle parts.I Asynchronous technology lends itself to high-level synthesis and modular design.The asynchronous community has made spectacular progress in the past decade, and today we know how to design correct and efficient asynchronous circuits. The correctness issue mostly concerned designing glitch-free circuits. The efficiency issue related to the cost of handshake protocols and completion detection.To appreciate this progress, consider the family of asynchronous chips designed at the California Institute of Technology between 1989 and 1999. Researchers at Caltech designed the world's first asynchronous microprocessor in 1989. The chip had 20,000 transistors and was a simple 16-bit machine. Its peak performance was 5 MIPS at 2 V drawing 10 mW, and 18 MIPS at 5 V drawing 225 mW, in 1.6-micron CMOS. It was correct on first silicon, and its performance was competitive with designs of that time.In 1994, Caltech presented an asynchronous, pipelined lattice structure filter, the first example of very fine pipelining. The chip had 250,000 transistors. In 0.9-micron CMOS and at 3.3 V, the throughput was 130 MHz-that is, 500 million 12-bit additions or multiplications per second. In liquid nitrogen, the filter executed 1 billion operations per second. The chip worked correctly from 1 V to 5 V. At 1.1 V, it operated at 36 million operations per second and consumed 20 mW.Between 1995 and...

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“…These range from building completely asynchronous chips [22,10,28] to various combinations of synchronous and asynchronous modules in the same design. We focus on the latter approach in this paper.…”

Section: Related Workmentioning

confidence: 99%