Efficient self-timed interfaces for crossing clock domains

Chakraborty, Anirban; Greenstreet, Mark R.

doi:10.1109/async.2003.1199168

Cited by 99 publications

(48 citation statements)

References 39 publications

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“…This method can achieve an acceptable data throughput [2], [3], and [4]. The architecture of FIFO is shown in figure (2). Because of data cells (empty/full detector) in FIFO architecture the silicon area is costly.…”

Section: A Fifo Solutionmentioning

confidence: 99%

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Design of a Self-Timed Data Synchronizer for Crossing Two Different Clock Domains

Zakaria¹,

Nawar²

2017

IJCA

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This paper presents asynchronous switch between any two different local clock synchronous domains. The asynchronous switch will generate a slower clock from two local clock modules and moderate the high rated clock domain to slow down its clock frequency without stopping or pausing any clock of them throughout the data communication among them. The proposed design is implemented using the CMOS 45nm technology of STMicroelectronics. In this case, the delay time to change the clock is shown to be about 0.4ns. The proposed system is designed to use a small number of circuit elements. Sothat, the asynchronous switch has a noticeable improvement in terms of power consumption, throughput, and circuit area.

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Section: A Fifo Solutionmentioning

confidence: 99%

“…Designer can use this solution to interconnect synchronous and asynchronous modules and also to construct synchronous-synchronous and asynchronous-asynchronous. This method can achieve an acceptable data throughput [2], [3], and [4]. The architecture of FIFO is shown in figure (2).…”

Section: A Fifo Solutionmentioning

confidence: 99%

Design of a Self-Timed Data Synchronizer for Crossing Two Different Clock Domains

Zakaria¹,

Nawar²

2017

IJCA

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“…for plesiosynchronous, rationally-related, and periodic clocks [8]- [10], or (ii) explores time-unbounded decision schemes such as pausible/stretchable clocking [11]- [13]. Few proposed "speculative" synchronization schemes do not target the clocking process itself as such but focus on overlapping synchronization with computation using architectural techniques [7], [14], [15].…”

Section: A Related Workmentioning

confidence: 99%

Metastability Tolerant Computing

Tarawneh

Függer

Lenzen

2017

2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

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Abstract-Synchronization using flip-flop chains imposes a latency of a few clock cycles when transferring data and control signals between clock domains. We propose a design scheme that avoids this latency by performing synchronization as part of state/data computations while guaranteeing that metastability is contained and its effects tolerated (with an acceptable failure probability). We present a theoretical framework for modeling synchronous state machines in the presence of metastability and use it to prove properties that guarantee some form of reliability. Specifically, we show that the inevitable state/data corruption resulting from propagating metastable states can be confined to a subset of computations. Applications that can tolerate certain failures can exploit this property to leverage low-latency and quasi-reliable operation simultaneously. We demonstrate the approach by designing a Network-on-Chip router with zerolatency asynchronous ports and show via simulation that it outperforms a variant with two flip-flop synchronizers at a negligible cost in packet transfer reliability.

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“…Synchronization can be achieved through the circuit for phase compensation adopting delay elements [5,6].…”

Section: Introductionmentioning

confidence: 99%

Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

Song¹,

Park²,

Lee³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-For the performance-efficient integration of IPs on an SoC utilizing heterochronous multi-clock domains, we propose a synchronization scheme that causes low latency overhead when data are crossing clock boundaries. The proposed synchronization scheme is composed of a clock predictor and a synchronizer. The clock predictor of a sender clock domain produces a predicted clock that is used in a receiver clock domain to detect possible synchronization failures in advance. When the possible synchronization failures are detected, a synchronizer at the receiver delays data-capture times to avoid the possible synchronization failures. From the simulation of the proposed scheme through SPICE modeling using a Chartered 0.18 mm CMOS process, we verified the functionalities and timing behavior of the clock predictor and the synchronizer. The simulation results show that the clock predictor produces a predicted clock before a synchronization failure, and the synchronizer samples data correctly using the predicted clock.

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Efficient self-timed interfaces for crossing clock domains

Abstract: With increasing integration densities, large chip designs

Cited by 99 publications

References 39 publications

Design of a Self-Timed Data Synchronizer for Crossing Two Different Clock Domains

Design of a Self-Timed Data Synchronizer for Crossing Two Different Clock Domains

Metastability Tolerant Computing

Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

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