Metastability Tolerant Computing

Abstract

Abstract-Synchronization using flip-flop chains imposes a latency of a few clock cycles when transferring data and control signals between clock domains. We propose a design scheme that avoids this latency by performing synchronization as part of state/data computations while guaranteeing that metastability is contained and its effects tolerated (with an acceptable failure probability). We present a theoretical framework for modeling synchronous state machines in the presence of metastability and use it to prove properties that guarantee some form of reliability. Specifically, we show that the inevitable state/data corruption resulting from propagating metastable states can be confined to a subset of computations. Applications that can tolerate certain failures can exploit this property to leverage low-latency and quasi-reliable operation simultaneously. We demonstrate the approach by designing a Network-on-Chip router with zerolatency asynchronous ports and show via simulation that it outperforms a variant with two flip-flop synchronizers at a negligible cost in packet transfer reliability.

Optimal Metastability-Containing Sorting via Parallel Prefix Computation

“…Obvious examples of such control loops are clock synchronization circuits, but MC has been shown to be useful for adaptive voltage control [13] and fast routing with an acceptable low probability of data corruption [29] as well. This type of application suggests to explore whether efficient circuits exist for a wider range of arithmetic operations, like e.g.…”

Xprova: Formal Verification Tool with Built-in Metastability Modeling

“…Therefore, the presence of a metastable event (a propagating sequence of timing violations) in the counter-example means that this event has explicitly caused the violation. In our counter-example, the T pin of k3 and V pin of R2 [3] are in an active state in cycle 3 and are therefore implicated in causing the violation (recall that these pins use active-X encoding). Examining the waveform, it appears that the data item 0x3A was received as 0x32 and that the mismatch occurred when data was latched by R2 during cycle 3.…”

“…We assume that this issue is not apparent at a first glance and proceed to verify the circuit by describing its behavior using the following Xprova properties: where Assumption 1 constrains the environment such that send remains high during a transfer and Assertion 1 states that the sent and received data items are equal. 3 Attempting to prove this specification using Xprova results in a fail status assigned to Assertion 1 and generates the counter-example shown in Figure 5.…”

“…(3) Generality: it can verify non-stereotypical designs, including those that violate standard practices [3];…”

Metastability-Containing Circuits

“…Metastability-Containing Circuits Many of the proposed techniques have been successfully employed to obtain metastability-aware TDCs [14], metastability-containing BRGC sorting networks [9,23], CMUXs [13], and metastability-tolerant network-on-chip routers [30]. Simulations verify the positive impact of metastability-containing techniques [9,13,30]. Most of these works channel efforts towards metastability-containing Field-Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) implementations of fault-tolerant distributed clock synchronization; this paper establishes that all required components are within reach.…”