An 0.18-μm CMOS for mixed digital and analog applications with zero-volt-V/sub th/ epitaxial-channel MOSFETs

Ohguro, T.; Naruse, H.; Sugaya, H.; Morifuji, E.; Nakamura, Shigenari; Yoshitomi, T.; Morimoto, T.; Kimijima, H.; Momose, H.S.; Katsumata, Y.

doi:10.1109/16.772479

Cited by 12 publications

(3 citation statements)

References 15 publications

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“…Figure 13 shows the ''normalized'' maximum transconductance (g m,max ϫ T ox /W) variation with the effective channel length for the SOS n-channel transistors used in this study. This normalized parameter is compared to those measured in bulk Si transistors by Taur et al 18 and Ohguro et al 19 The normalized g m of SOS transistors exhibits a higher value than in bulk Si ͑without epitaxial channel͒ whatever the channel length is. A difference as large as 45% has been noticed for an effective channel length of 0.2 m. This difference is due to the good value of effective carrier mobility, as mentioned in a previous section.…”

Section: Rf Measurementsmentioning

confidence: 83%

Characterization of Silicon-on-Sapphire Material and Devices for Radio Frequency Applications

Munteanu¹,

Cristoloveanu²,

Rozeau³

et al. 2001

J. Electrochem. Soc.

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Recently fabricated silicon-on-sapphire ͑SOS͒ wafers show improved electrical properties. This was demonstrated by both wafer and device-level characterization, in a wide range of temperatures ͑from 20 to 400 K͒. We discuss Hall effect measurements in bare SOS wafers as well as transistor properties in n-and p-channels ͑mobility, threshold voltage, subthreshold swing, and leakage currents͒. The short-channel effects are investigated in terms of charge sharing, drain-induced barrier lowering and fringing fields. Nonstatic measurements reveal a very long drain current overshoot at low temperature. Additional radio frequency measurements show excellent performance in the microwave domain.The explosive development of mobile communications requires high-quality microwave circuits with increasingly higher levels of integration. Silicon-on-sapphire ͑SOS͒ technology has shown great potential for high-frequency/radio-frequency ͑rf͒ applications. As compared with modern silicon-on-insulator ͑SOI͒ materials ͑SI-MOX, Unibond͒, SOS offers numerous advantages, such as 1 1. A quasi-infinitely thick isolating Al 2 O 3 substrate, reducing microwave losses and making SOS an ideal candidate for integration of rf circuits for wireless communications.2. 30 times higher thermal conductivity in sapphire than in SiO 2 , which allows better thermal dissipation through the substrates and reduces self-heating effects. 2,3 3. Low carrier lifetime, leading to a reduced gain of the parasitic bipolar transistor ͓therefore improved breakdown voltage of complementary metal-oxide semiconductor ͑CMOS͒ circuits, attenuated floating-body effects, and shorter transients͔. 4 4. It is a low-cost technological process. SOS also features important advantages over bulk silicon, essentially lower junction capacitances, better radiation hardness, and higher density of integration. At present, the use of SOS technology becomes an attractive solution for considerably improving the performances of silicon rf-integrated circuits. 2 Indeed, SOS allows the elaboration of passive components, such as inductors, with good performances compared to that fabricated on silicon substrates. Johnson et al. have shown high self-resonant frequencies and high quality factors of inductors fabricated on sapphire substrate (Q peak ϭ 9.9 and f sr ϭ 7 GHz for L ϭ 5.4 nH). 5 In the past, the SOS technology was handicapped mainly by the low-volume production, strain effects affecting the carrier mobility, and poor quality of the Si/Al 2 O 3 interface. 6 As-grown Si films on sapphire contained also a high defect density. These drawbacks have been reduced thanks to a continuous improvement in the implantation process and solid-phase epitaxial regrowth. Consequently, SOS wafers with reasonable crystal quality, very thin films ͑ϳ100 nm͒ and 6-8 in. wafer size are now available.This paper presents a detailed investigation of the electrical properties in recent SOS materials and devices, at low and high temperatures and in the microwave regime. Characterization of As-Grown SOS Films by Ha...

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Section: Rf Measurementsmentioning

confidence: 83%

Characterization of Silicon-on-Sapphire Material and Devices for Radio Frequency Applications

Munteanu¹,

Cristoloveanu²,

Rozeau³

et al. 2001

J. Electrochem. Soc.

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“…In comparison to standard MOSFET devices, they have higher transconductance to gate oxide capacitance (g m =C OX ) peak. 1) These devices are used in electro static discharge (ESD), 2) voltage multipliers, ASK demodulators, 3) RF and analog applications, 4,5) high speed circuits, voltage regulators, multiplexers, 6) input=output circuits, 7) input buffer circuits, 8) opamp for bio-medical applications, 9) bandgap reference (BGR) circuits, 10) current reference circuits 11) etc. To capture the correct behavior of zero-V TH MOSFET devices, there is a need of a computationally efficient compact model which can account for all real device effects.…”

Section: Introductionmentioning

confidence: 99%

Analysis and modeling of zero-threshold voltage native devices with industry standard BSIM6 model

Gupta

Agarwal

Lin

et al. 2017

Jpn. J. Appl. Phys.

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In this paper, we present the modeling of zero-threshold voltage (VTH) bulk MOSFET, also called native devices, using enhanced BSIM6 model. Devices under study show abnormally high leakage current in weak inversion, leading to degraded subthreshold slope. The reasons for such abnormal behavior are identified using technology computer-aided design (TCAD) simulations. Since the zero-VTH transistors have quite low doping, the depletion layer from drain may extend upto the source (at some non-zero value of VDS) which leads to punch-through phenomenon. This source–drain leakage current adds with the main channel current, causing the unexpected current characteristics in these devices. TCAD simulations show that, as we increase the channel length (Leff) and channel doping (NSUB), the source–drain leakage due to punch-through decreases. We propose a model to capture the source–drain leakage in these devices. The model incorporates gate, drain, body biases and channel length as well as channel doping dependency too. The proposed model is validated with the measured data of production level device over various conditions of biases and channel lengths.

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“…We consider that Si-based silicon-on-insulator ͑SOI͒ MOSFETs have large potential for rf applications because device performance will be strongly advanced as device dimensions are aggressively reduced in the future. 3 It is known that the double-gate ͑DG͒ SOI MOSFET [4][5][6][7] and the groundplane ͑GP͒ SOI MOSFET [8][9][10] offer high immunity against shortchannel effects. However, these devices still have a couple of issues.…”

mentioning

confidence: 99%

Silicon-on-Insulator MOSFET Structure for Sub-100 nm Channel Regime and Performance Perspective

Ōmura

2001

J. Electrochem. Soc.

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This paper describes performances of the partial-ground-plane ͑PGP͒ silicon-on-insulator metal-oxide semiconductor field effect transistor aiming at the demanding radio-frequency applications of the future. In the PGP device, short-channel effects are suppressed by terminating most of the source-and drain-induced electric fields to small heavy doping regions that are localized below the source and drain regions. As a result, the sub-100 nm PGP device with appropriately designed heavy doping regions minimizes the influence of the source and drain parasitic capacitance, even if thin buried oxide layers are used.It is considered that for radio-frequency ͑rf͒ applications bipolar transistors and compound semiconductor devices are superior to conventional metal-oxide semiconductor field effect transistors ͑MOSFETs͒ from the viewpoints of high-frequency operation and noise characteristics. 1 Bipolar transistors, however, suffer from significant base current loss and more complexity in terms of device miniaturization; compound semiconductor devices need complex fabrication processes with high material costs. 2 These problems limit their use in consumer electronics. We consider that Si-based silicon-on-insulator ͑SOI͒ MOSFETs have large potential for rf applications because device performance will be strongly advanced as device dimensions are aggressively reduced in the future. 3 It is known that the double-gate ͑DG͒ SOI MOSFET 4-7 and the groundplane ͑GP͒ SOI MOSFET 8-10 offer high immunity against shortchannel effects. However, these devices still have a couple of issues. Most GP-SOI MOSFETs have a very large subthreshold swing, 8 and the threshold voltage of n ϩ -poly-Si DG-SOI n-channel MOSFETs is usually very low, 5,6 while threshold voltage of p ϩ -poly-Si DG-SOI n-channel MOSFETs is comparatively high. 7 DG-SOI MOSFETs also have many weaknesses from the viewpoint of the process technology. Consequently, issues remain in achieving practical shortchannel SOI MOSFETs. This paper discusses a new SOI device structure that can realize sub-100 nm channel devices. This structure gives us a practical approach to the development of sub-100 nm channel single-gate SOI device technology. DC and rf characteristics of the proposed structure are simulated 11 in a comparison to conventional single-gate and GP-SOI MOSFETs. Design issues of the new device are also discussed. Device StructureThe proposed device structure, shown in Fig. 1, is called the partial-ground-plane ͑PGP͒ SOI MOSFET. The PGP structure has two heavy doping regions below the buried oxide layer near the source and drain regions. These heavy doping regions, called PGP regions, have doping levels of the order of 10 20 cm Ϫ3 . The PGP regions suppress short-channel effects ͑SCEs͒ by controlling the electric field around the p-n junction regions. Parameter L 1 is the space between the PGP region and the source or drain junction edge. PGP region width is L 2 . The simulations in this paper assume that L 2 is 10 nm and PGP region depth is 10 nm. Since L 2 is smaller th...

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An 0.18-μm CMOS for mixed digital and analog applications with zero-volt-V/sub th/ epitaxial-channel MOSFETs

Cited by 12 publications

References 15 publications

Characterization of Silicon-on-Sapphire Material and Devices for Radio Frequency Applications

Characterization of Silicon-on-Sapphire Material and Devices for Radio Frequency Applications

Analysis and modeling of zero-threshold voltage native devices with industry standard BSIM6 model

Silicon-on-Insulator MOSFET Structure for Sub-100 nm Channel Regime and Performance Perspective

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