An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

Abstract

This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less than 5% power overhead. Moreover, the implemented multi-stage topology significantly advances the state-of-the-art comparator performance, achieving the highest reported operating frequency, as well as the lowest delay slope and sensitivity to supply and common mode variations compared to existing works, with similar energy/comparison. This makes the proposed self-calibrating comparator an ideal candidate for high resolution (>10 b) multi-GHz Analog-to-Digital Converters (ADCs). The 28 nm bulk CMOS prototype measures an input-referred noise and calibrated offset of 0.82 mV and 0.99 mV, respectively clocked at 11 GHz, consuming only 0.89 mW from a 1 V supply, for an area of 0.00054 mm 2 , including calibration.

Signal Processing and Analysis of Electrical Circuit

“…The self-calibrating dynamic comparator was developed. The presented approach reduced the input offset by 10× [10]. There are also other interesting articles in the presented special issue.…”

High-Performance Dynamic Comparator

“…A dynamic comparator has a preamplifier stage in which two analog inputs are applied to the two corresponding input terminals for comparison. The analog input that is supplied to the input terminals can be performed either by using a single analog voltage source or by using two analog voltage sources [4], [5]. The number of input sources determines the modes of operation are prescribed as common mode and differential mode respectively.…”

“…The preamplifier stage in Elzaker is identical to the preamplifier stage in the double-tail dynamic comparator. Elzaker comparator uses six transistors to design latch for A/D conversion whereas double tail dynamic comparator uses only five transistors [4], [5], [9].…”

Analysis of strong-arm comparator with auxiliary pair for offset calibration

“…The Strong-Arm comparator with offset calibration using auxiliary pair is often used in practical designs [11][12][13]. It has the advantages of simple circuit structure, tiny additional load capacitance, zero static power consumption, etc.…”