1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers 1991
DOI: 10.1109/isscc.1991.689117
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An 11-million Transistor Neural Network Execution Engine

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Cited by 54 publications
(15 citation statements)
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“…The CNAPS2 architecture is a Single-Instruction Multiple-Data (SIMD) array ofprocessors[7J [8]. The design uses multiple processing nodes (PNs) that execute the same operation on different values.…”
Section: The Cnaps Architecturementioning
confidence: 99%
“…The CNAPS2 architecture is a Single-Instruction Multiple-Data (SIMD) array ofprocessors[7J [8]. The design uses multiple processing nodes (PNs) that execute the same operation on different values.…”
Section: The Cnaps Architecturementioning
confidence: 99%
“…2 The CNAPS chip has 64 PNs on each chip, and has 4 Kbytes of static RAM local to eh PN. 2 The CNAPS chip has 64 PNs on each chip, and has 4 Kbytes of static RAM local to eh PN.…”
Section: Chip Implementationmentioning
confidence: 99%
“…([Pomerlau et al (1988)], [Iwata et al (1990)], [Griffin et al (1991)] and [Wawrzynek et al (1993)]) and consequently, this leads to costly and inefficient computations. Therefore, model reduction is of paramount importance.…”
Section: Introductionmentioning
confidence: 99%