An 18-mW 1.175–2-GHz Frequency Synthesizer With Constant Bandwidth for DVB-T Tuners

Lü, Lei; Chen, Jinghong; Lei, Yuan; Min, Hao; Tang, Zihui

doi:10.1109/tmtt.2009.2014449

Cited by 48 publications

(4 citation statements)

References 25 publications

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“…Figure 6 shows the simulated Q factor of varactors in the proposed VCO and conventional varactors in Ref. [6]. The varators are switched on and controlled by V ctrl .…”

Section: Vcomentioning

confidence: 99%

A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-QLC-VCO

Cao¹,

Yang²,

Tan³

et al. 2011

J. Semicond.

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A phase-locked loop (PLL) frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator (VCO) is presented. The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations. The Q factor of the inductor, I-MOS capacitors and varactors in the VCO are optimized. The proposed frequency synthesizer was fabricated by SMIC 0.13 m 1P8M MMRF CMOS technology with a chip area of 1150 2500 m 2 . When locking at 5 GHz, the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz.

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“…Figure 6 shows the simulated Q factor of varactors in the proposed VCO and conventional varactors in Ref. [6]. The varators are switched on and controlled by V ctrl .…”

Section: Vcomentioning

confidence: 99%

A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-QLC-VCO

Cao¹,

Yang²,

Tan³

et al. 2011

J. Semicond.

View full text Add to dashboard Cite

show abstract

“…[7][8][9][10][11][12][13] The LC-PLLs show superior phase-noise performance at the cost of large area. LC oscillators need a multiple-switched-capacitors array [14][15][16] and auto-frequency calibration (AFC) [17][18][19] techniques to expand the tuning range, which raise the design complexity of the PLL. The RPLL is more attractive than the LC-PLL for SoC applications because it has the advantages of small area and large tuning range, but the phase noise is much worse than that of the LC-PLL, and may greatly degrade the jitter performance.…”

Section: Introductionmentioning

confidence: 99%

Compact 0.3-to-1.125 GHz self-biased phase-locked loop for system-on-chip clock generation in 0.18 µm CMOS

Zhang¹,

Liu²,

Feng³

et al. 2016

Jpn. J. Appl. Phys.

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In this paper, we propose a compact ring-oscillator-based self-biased phase-locked loop (SBPLL) for system-on-chip (SoC) clock generation. It adopts the proposed triple-well NMOS source degeneration voltage-to-current (V–I) converter instead of the operational amplifier (OPAMP) based V–I converter and a proposed simple start-up circuit with a negligible area to save power and area. The SBPLL is implemented in the 0.18 µm CMOS process, and it occupies 0.048 mm2 active core. The measurement results show the SBPLL can generate output frequency in a wide range from 300 MHz to 1.125 GHz with a constant loop bandwidth that is around 5 MHz and a relatively low jitter performance that is less than 4.9 mUI over the entire covered frequency range. From −20 to 70 °C the rms jitter variation and loop bandwidth variation at 1.125 GHz are 0.2 ps and 350 kHz, respectively. The rms jitter performance variation of all covered frequency points is less than 10% in the supply range from 1.5 to 1.7 V. Such SBPLL shows robustness over environmental variation. The maximum power consumption is 5.6 mW with 1.6 V supply at an output frequency of 1.125 GHz.

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“…References [10,11] solve this problem by adding a selfcontrolled varactor array. Reference [12] uses 16 tuning curves to achieve constant K VCO and f step , but it relies on an arbitrary scaling capacitor array, which makes this method hard to extend to more curves. Reference [13] provides a pseudoexponential capacitor array method.…”

Section: Introductionmentioning

confidence: 99%

“…Based on Refs. [9][10][11][12][13], the VCO of this work employs 128 tuning curves to cover a range of 1.4-2.2 GHz, nearly a 44.4% tuning range. Besides, a selfcontrolled varactor array is added in the VCO to compensate for variation of K VCO and f step .…”

Section: Introductionmentioning

confidence: 99%

A 220–1100 MHz low phase-noise frequency synthesizer with wide-band VCO and selectable I/Q divider

Chen¹,

Renjie²,

Xu³

et al. 2014

J. Semicond.

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This paper presents a low phase-noise fractional-N frequency synthesizer which provides an in-phase/quadrature-phase (I/Q) signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation (WIA) applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator (VCO) is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 kHz loop bandwidth, lowest measured phase noise is −106 dBc/Hz at a 10 kHz offset and −131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 μm CMOS process, the synthesizer occupies a chip area of 1.2 mm2, consumes only 15 mW from the 1.8 V power supply, and settles within 13.2 μs. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.

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An 18-mW 1.175–2-GHz Frequency Synthesizer With Constant Bandwidth for DVB-T Tuners

Cited by 48 publications

References 25 publications

A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-QLC-VCO

A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-QLC-VCO

Compact 0.3-to-1.125 GHz self-biased phase-locked loop for system-on-chip clock generation in 0.18 µm CMOS

A 220–1100 MHz low phase-noise frequency synthesizer with wide-band VCO and selectable I/Q divider

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