Compact 0.3-to-1.125 GHz self-biased phase-locked loop for system-on-chip clock generation in 0.18 µm CMOS

Abstract

In this paper, we propose a compact ring-oscillator-based self-biased phase-locked loop (SBPLL) for system-on-chip (SoC) clock generation. It adopts the proposed triple-well NMOS source degeneration voltage-to-current (V–I) converter instead of the operational amplifier (OPAMP) based V–I converter and a proposed simple start-up circuit with a negligible area to save power and area. The SBPLL is implemented in the 0.18 µm CMOS process, and it occupies 0.048 mm2 active core. The measurement results show the SBPLL can generate output frequency in a wide range from 300 MHz to 1.125 GHz with a constant loop bandwidth that is around 5 MHz and a relatively low jitter performance that is less than 4.9 mUI over the entire covered frequency range. From −20 to 70 °C the rms jitter variation and loop bandwidth variation at 1.125 GHz are 0.2 ps and 350 kHz, respectively. The rms jitter performance variation of all covered frequency points is less than 10% in the supply range from 1.5 to 1.7 V. Such SBPLL shows robustness over environmental variation. The maximum power consumption is 5.6 mW with 1.6 V supply at an output frequency of 1.125 GHz.

A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications

“…Different devices transmit different carrier frequencies; therefore, PLLs with high accuracy, high stability, fast switching speed, and low power are necessary. 1,5,[13][14][15][16][17] In a conventional analog PLL, the circuit supplies current using the charge pump, converts the current into a voltage to control the voltage-controlled oscillator, and uses passive components. 3,13,18) Therefore, additional time is required to redesign the circuit when it is used with a technology that uses a different process.…”

All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application

“…A clock with an accurate 50% duty cycle is crucial in modern high-speed circuits and systems. Applications such as memory, [1][2][3][4] double sampling analog-to-digital converters (ADC), [5][6][7][8][9][10] transceivers (Tx=Rx), [11][12][13][14][15] and system-on-a-chip (SoC), [15][16][17] use both positive and negative transition edges for double data transfer rate. Therefore, a clock with non-50% duty cycle directly degrades performance, thereby necessitating the use of a duty-cycle corrector (DCC), [18][19][20][21][22][23][24] as shown in Fig.…”