An 8–18 GHz power amplifier with novel gain fluctuation compensation technique in 65 nm CMOS

Abstract

A wideband CMOS power amplifier with high gain and excellent gain flatness for X–Ku-band radar phased array is proposed in this paper. Excellent gain flatness is achieved with transformer based matching networks (TMNs), in which the gain fluctuation of an inter-stage matching network can be compensated by the proposed design methods. The circuit is fabricated in the TSMC 65 nm RF CMOS process. The proposed technique is verified by the measurement results, which show that the wideband PA achieves gain of 21–22.5 dB with only ±0.75 dB gain fluctuation and 13–14.6 dBm flat output power between 7.5 and 15.5 GHz, and a little more ripple in the rest of the X–Ku band due to the inaccuracy of passive modelling at high frequency. The circuit delivers saturated and 1 dB-compressed output power of 14.6 and 11.3 dBm respectively at 13 GHz, for a maximal power-added efficiency (PAE) of 23%.

Analytical modelling of ultra‐small group delay variation of ultra‐broadband RF power amplifier using NSGA‐II algorithm

“…Many CMOS PAs have been reported in the published articles. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15] One of the earliest CMOS PA presented GD variation of ±250 ps, which is too high. 1 A 3.1-6 GHz CMOS PA based on cascode amplifier with resistive shunt feedback topology offering forwarded gain (S 21 ) of 10 ± 1 dB and achieved a GD variation of ±195.5 ps.…”

“…Meanwhile, it also achieved the gain, Psat and PAE of 20.65%, 13.9% and 20% at 15.5 GHz, respectively. An 8–12 GHz PA is designed using two stage cascode topology with transformer based inter‐stage matching network that helps to achieve an excellent gain flatness of 21.75 ± 0.75 dB with maximum PAE and Pout of 23% and 14.6 dBm at 13 GHz, respectively 11 …”

“…Thus, output signal does not retain its original identity without a PA having small GD variation, which gives motivation to design the PA with small GD variation over ultra‐broad band applications. Many CMOS PAs have been reported in the published articles 1–15 . One of the earliest CMOS PA presented GD variation of ±250 ps, which is too high 1 .…”

“…An 8-12 GHz PA is designed using two stage cascode topology with transformer based inter-stage matching network that helps to achieve an excellent gain flatness of 21.75 ± 0.75 dB with maximum PAE and Pout of 23% and 14.6 dBm at 13 GHz, respectively. 11 Therefore, this article proposes a ± 9.4 ps small GD variation of CMOS PA over ultra-broadband of 6.5-17 GHz is presented. NSGA-II multi-objective algorithm is employed to achieve various performance parameters of the proposed PA.…”

A 0.1–1.5 GHz multi-octave quadruple-stacked CMOS power amplifier

“…Modern wireless communication systems working in 0.1-1.5 GHz have recently been developed, such as industrial scientific and medical (ISM), enterprise network, space and so on, which results in the desirability of a single chip CMOS transceiver to urgently reduce the overall cost. As a key component in the RF transceiver, there are still many challenges for the CMOS power amplifier (PA) design, which are mainly caused by the low breakdown voltage and lossy on-chip passive elements [1,2] .…”