An 8-b 1GS/s Fractional Folding CMOS Analog-to-Digital Converter with an Arithmetic Digital Encoding Technique

Abstract

Abstract-A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is 2.1 mm 2 (ADC core : 1.4 mm 2 , calibration engine : 0.7 mm 2 ), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.

A 45 nm 9-bit 1 GS/s High Precision CMOS Folding A/D Converter with an Odd Number of Folding Blocks

“…Most of the ADCs have some drawbacks of linearity error, gain error, and a few errors due to device mismatching and other secondary effects. Hence, many ADCs recently have the self-calibration logic to reduce the errors [17]. But, since there is no calibration circuit in this ADC, the measured performance is not good.…”

“…Thus a folding structure using an odd number of folding blocks and the preamp is discussed to solve the asymmetric error. Conventionally, the 2 nd folding-interpolation stage is based on the even number of interpolation rate(IR=4) in [17]. However, it has a drawback that the zero-crossing cannot generate the perfect symmetrical codes of ADC.…”