An 8-b 20-Msample/s pipelined A/D converter in 0.5-/spl mu/m CMOS with 7.8 ENOB

Savengsveksa, V.; Heediley, P.L.; Matthews, T.W.; Ahmad, K. J.; Negrete, J.

doi:10.1109/mwscas.2005.1594124

Search citation statements

Order By: Relevance

Paper Sections

Select...

Comparator1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2006

2008

Publication Types

Select...

Other3

Article2

Relationship

Self Cite0

Independent5

Authors

Journals

Cited by 5 publications

(1 citation statement)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A swing-minimizing circuit (SMC) similar to the one in [8] as shown in Fig. 7 was used to reduce the swing of CLK1sm.…”

Section: Comparatormentioning

confidence: 99%

A 30-mW 8-b 125-MS/s pipelined ADC in 0.13-μm CMOS

Heedley

Dyer

Matthews

et al. 2008

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

An 8-b pipelined ADC constructed in 0.13-lm CMOS is described. This ADC uses a dual-supply technique to yield 8-b performance at a sampling rate of 125 MS/s while consuming 30 mW from 1.8-V and 1.2-V supplies. Active area is 0.4 mm 2 . Numerous challenges associated with this choice of process technology were overcome, such as limited dynamic range, copper metallization and the effects of gate oxide leakage.

show abstract

“…A swing-minimizing circuit (SMC) similar to the one in [8] as shown in Fig. 7 was used to reduce the swing of CLK1sm.…”

Section: Comparatormentioning

confidence: 99%