Abstract-A simulation method that has proven valuable in the design of high-speed regenerative comparators such as those used in pipeline and flash analog-to-digital converters is presented. This method yields an input-referred offset voltage for the comparator while it is operating at speed, including both DC and dynamic effects such as charge injection and capacitive coupling. The speed and efficiency of the method allows the circuit designer to more fully explore the design space, and provides important insights into comparator operation.
This paper describes a new approach to the mentoring of graduate students through their master's projects recently developed at California State University, Sacramento in the area of integrated circuit (IC) design. Student engineering teams were formed to design, layout and test two separate pipelined analog-to-digital converter chips and a specialized biomedical chip. The goal of each team was to build a complex mixed-signal system on a chip comprising several diverse circuit blocks, with each student taking responsibility for a particular block. The students were guided through a complete industrial style IC design flow, including architecture, design and layout reviews. The unique challenge of this approach for the instructor is to guide the students to design their individual blocks while insuring that the overall system requirements are met. For the students, the advantages of this approach include the experience of working together as a team, the ability to work on larger designs than a single student could do alone, and the understanding gained of several different circuit blocks. The methodology and pedagogical techniques developed for this approach as well as a number of challenges which were overcome along the way will be described. An overall assessment will be presented based on technical results achieved, student exit interviews and feedback from industry experts.
An 8-b pipelined ADC constructed in 0.13-lm CMOS is described. This ADC uses a dual-supply technique to yield 8-b performance at a sampling rate of 125 MS/s while consuming 30 mW from 1.8-V and 1.2-V supplies. Active area is 0.4 mm 2 . Numerous challenges associated with this choice of process technology were overcome, such as limited dynamic range, copper metallization and the effects of gate oxide leakage.
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