An 8-bit 200 MS/s CMOS folding/interpolating ADC with a reduced number of preamplifiers using an averaging technique

Abstract

An 8-bit 200MSamplds CMOS fnldinglinterpolating ADC chip was implemented by using a 0.35double-poly CMOS prncess. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array in comparison with the published fnldinglinterpnlating ADC chips. The delay time of digital encoder block was reduced to 1.311s from 2.211.5 by using a DCVSPG-style diflerential logic. The chip area and the measured power Consumption were 1.02 nun' and 12OmW respectively at the supply voltage of3JV.