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A digital differential transmitter based on CMOS inverter worked up to 2.8 Gbps at the supply voltage of 1 V with a 0.18 μm CMOS process. By calibrating the output impedance of the transmitter, the impedance matching between the transmitter output and the transmission line is achieved. The PVT variations of pre-driver are compensated by the calibration of the rising-edge delay and falling-edge delay of the pre-driver outputs. The chip fabricated with a 0.18 μm CMOS process, which uses the standard supply voltage of 1.8 V, gives the highest data rate of 4 Gbps at the supply voltage of 1.2 V. The proposed calibration schemes improve the eye opening with the voltage margin by 200% and the timing margin by 30%, at 2.8 Gbps and 1 V.

An 8-bit 200MSamplds CMOS fnldinglinterpolating ADC chip was implemented by using a 0.35double-poly CMOS prncess. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array in comparison with the published fnldinglinterpnlating ADC chips. The delay time of digital encoder block was reduced to 1.311s from 2.211.5 by using a DCVSPG-style diflerential logic. The chip area and the measured power Consumption were 1.02 nun' and 12OmW respectively at the supply voltage of3JV.