An 8-bit 400-MS/s calibration-free SAR ADC with a pre-amplifier-only comparator

Hou, Chih-Huei; Chang, Soon-Jyh; Wu, Honggang; Hu, Huan-Jui; Cun, En-Ze

doi:10.1109/vlsi-dat.2017.7939660

Cited by 4 publications

(5 citation statements)

References 5 publications

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“…The proposed circuit entailed on three modes, including one amplification and two comparisons, which is controlled by a centralized spider-latch with the assistance of switches. The proposed design is utterly calibration-free because the time control scheme is used for reset and comparisons as in Hou et al (2017). The simplified block diagrams of the complete project are shown in Figures 1 and 2.…”

Section: Proposed Solutionmentioning

confidence: 99%

“…The speed of capacitors can rise when the time using tunable delay lines is minimized (Malki et al, 2014). Additionally, we can use a conventional timing scheme to make a comparator/amplifier efficient, faster and accurate (Hou et al, 2017).…”

Section: Introductionmentioning

confidence: 99%

“…To obtain less delay at the gate of the transistors, one sampling switch and a shared DAC can be used because of low settling time requirement in ADC (Hou et al, 2017). To improve the delay in comparison, the input and cross-coupled NMOS transistors' trans-conductance can be measured as in Xin et al (2017).…”

Section: Introductionmentioning

confidence: 99%

“…Comparator offset mismatches and broader tolerances can be achieved by using the redundancy algorithm (Hou et al, 2017). Besides this, to get better overdrive recovery speed, we need to minimize the trade-off between gain and power dissipation.…”

Section: Introductionmentioning

confidence: 99%

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Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Faheem

Zhong

Wang

et al. 2020

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Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

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Section: Proposed Solutionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Faheem

Zhong

Wang

et al. 2020

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“…The processing speed of the comparator is directly proportional to the charging time of its capacitor. It can be improved by planting the tuneable delay lines (Malki et al, 2014) and conventional-timing scheme (Hou et al, 2017). To achieve the miniaturization parameter, these are not favorable solutions due to covering a new area on a silicon chip.…”

mentioning

confidence: 99%

Bio-inspired circuitry of bee-bootstrap and Spider-latch comparator for ultra-low power SAR-ADC

Faheem

Zhong

Wang

et al. 2021

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Purpose There are many types of the ADCs implemented in the mobile and wireless devices. Most of these devices are battery operated and operational at low input voltage. SAR ADC is popular for its low power operations and simple architecture. Scientists are still working to make its working faster under the same low power area. There are many SAR-ADC implemented in the past two decades, but still, there is a big room for dual SAR-ADC. Design/methodology/approach The authors are presenting a dual SAR-ADC with a smaller number of components and blocks. The proposed ultra-low-power circuit of the SAR-ADC consists of four major blocks, which include Bee-bootstrap, Spider-Latch dual comparator, dual SAR-logic and dual digital to analog converter. The authors have used the 90-nm CMOS library for the construction of the design. Findings The power breaks down of the comparator are dramatically improved from 0.006 to 0.003 uW. The ultimate design has 5 MHz operating frequency with 25 KS/s sampling frequency. The supply voltage is 1.2 V with 35.724 uW power consumption. Signal-to-noise and distortion ratio and spurious-free dynamic range are 65 and 84 dB, respectively. The Walden's figure of merits calculated 7.08 fj/step. Originality/value The authors are proposing two-in-one circuit for SAR-ADC named as “dual SAR-ADC”, which obeys the basic equation of duality, derived and proved under the heading of proposed solution. It shows a clear difference between the performance of two circuit-based ADC and one dual circuit ADC. The number of components is reduced by sharing the work load of some key components.

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A low-power, high-resolution, 1 GHz differential comparator with low-offset and low-kickback

Aldacher

Nasrollahpour

Hamedi-Hagh

2017

2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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An 8-bit 400-MS/s calibration-free SAR ADC with a pre-amplifier-only comparator

Cited by 4 publications

References 5 publications

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Bio-inspired circuitry of bee-bootstrap and Spider-latch comparator for ultra-low power SAR-ADC

A low-power, high-resolution, 1 GHz differential comparator with low-offset and low-kickback

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