An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping

Zhang, Yewei; Huang, Kejie; Xiao, Rui; Shen, Haibin

doi:10.1109/tvlsi.2022.3140395

Cited by 9 publications

(7 citation statements)

References 35 publications

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“…The higher four bits and lower four bits are jointed by the charge redistribution between two capacitors in the two integrators with a ratio of 16:1. The significance of the input data is also realized by averaging the charge between integrators and ADC [50]. The simulation waveform of the integration and charge sharing process is shown in Fig.…”

Section: Domino Rofmmentioning

confidence: 99%

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Domino: A Tailored Network-on-Chip Architecture to Enable Highly Localized Inter- and Intra-Memory DNN Computing

Zhou¹,

Yangshuo²,

Xiao³

et al. 2021

Preprint

Self Cite

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The ever-increasing computation complexity of fast-growing Deep Neural Networks (DNNs) has requested new computing paradigms to overcome the memory wall in conventional Von Neumann computing architectures. The emerging Computing-In-Memory (CIM) architecture has been a promising candidate to accelerate neural network computing. However, the data movement between CIM arrays may still dominate the total power consumption in conventional designs. This paper proposes a flexible CIM processor architecture named Domino to enable stream computing and local data access to significantly reduce the data movement energy. Meanwhile, Domino employs tailored distributed instruction scheduling within Network-on-Chip (NoC) to implement inter-memory-computing and attain mapping flexibility. The evaluation with prevailing CNN models shows that Domino achieves 1.15-to-9.49× power efficiency over several stateof-the-art CIM accelerators and improves the throughput by 1.57-to-12.96×.

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Section: Domino Rofmmentioning

confidence: 99%

“…The interface between analog domain and digital domain also contributes to high power consumption. [50] proposes a binary input pattern for CIM, instead of a high power consumption DAC, to reduce the interface energy. In this way, both computing efficiency and reliability are improved.…”

Section: Related Workmentioning

confidence: 99%

Domino: A Tailored Network-on-Chip Architecture to Enable Highly Localized Inter- and Intra-Memory DNN Computing

Zhou¹,

Yangshuo²,

Xiao³

et al. 2021

Preprint

Self Cite

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show abstract

“…The computing efficiency of the CIM core is limited to 0.61 TOPS/s/W. To address this issue, Y Zhang et al [13] proposed an 8-bit In Resistive Memory Computing Core with Regulated Passive Neuron and Bit Line Weight Mapping (RPN & BLM) scheme. RPN & BLM uses passive integral circuits without amplifiers to decrease power consumption.…”

Section: B Digitized Rram Based Cim Coresmentioning

confidence: 99%

“…The stimulus will turn on the transistor in 1R1T to generate the current to pass through RRAM cells and accumulated at the integrators to enable the massive parallel MAC computation. Regulator [13] is used before the integrator to minimize the voltage variation caused by the channel length modulation during the integration. Finally, the analog voltage at the neuron is converted to the digital signals using the charge redistribution differential SAR ADC.…”

Section: Differential Weight Based Cim Coresmentioning

confidence: 99%

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A Low Power In-Memory Multiplication andAccumulation Array with Modified Radix-4 Inputand Canonical Signed Digit Weights

Xiao,

Huang,

Zhang

et al. 2021

Preprint

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A mass of data transfer between the processing and storage units has been the leading bottleneck in modern Von-Neuman computing systems, especially when used for Artificial Intelligence (AI) tasks. Computing-in-Memory (CIM) has shown great potential to reduce both latency and power consumption. However, the conventional analog CIM schemes are suffering from reliability issues, which may significantly degenerate the accuracy of the computation. Recently, CIM schemes with digitized input data and weights have been proposed for high reliable computing. However, the properties of the digital memory and input data are not fully utilized. This paper presents a novel low power CIM scheme to further reduce the power consumption by using a Modified Radix-4 (M-RD4) booth algorithm at the input and a Modified Canonical Signed Digit (M-CSD) for the network weights. The simulation results show that M-Rd4 and M-CSD reduce the ratio of 1 × 1 by 78.5% on LeNet and 80.2% on AlexNet, and improve the computing efficiency by 41.6% in average. The computing-power rate at the fixed-point 8-bit is 60.68 TOPS/s/W.

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An Energy-Efficient Mixed-Bit ReRAM-based Computing-in-Memory CNN Accelerator with Fully Parallel Readout

Liu

Mao

Zhou

et al. 2022

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

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An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping

Cited by 9 publications

References 35 publications

Domino: A Tailored Network-on-Chip Architecture to Enable Highly Localized Inter- and Intra-Memory DNN Computing

Domino: A Tailored Network-on-Chip Architecture to Enable Highly Localized Inter- and Intra-Memory DNN Computing

A Low Power In-Memory Multiplication andAccumulation Array with Modified Radix-4 Inputand Canonical Signed Digit Weights

An Energy-Efficient Mixed-Bit ReRAM-based Computing-in-Memory CNN Accelerator with Fully Parallel Readout

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