An 8-Core 64-Thread 64b Power-Efficient SPARC SoC

Nawathe, U.M.; Hassan, Mahmudul; Warriner, L.; Yen, King C.; Upputuri, B.; Greenhill, D.; Kumar, Ashok; Park, H.

doi:10.1109/isscc.2007.373611

Cited by 71 publications

(29 citation statements)

References 1 publication

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“…The 8-and 16-core Sun Niagara [17] and Niagara2 [24] chips use electrical crossbars. The 80-core Intel Polaris chip [31] and the 64-core MIT Raw processor [29] connect their cores with 2D mesh networks.…”

Section: Related Workmentioning

confidence: 99%

Corona: System Implications of Emerging Nanophotonic Technology

Vantrease

Schreiber

Monchiero

et al. 2008

2008 International Symposium on Computer Architecture

429

479

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We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance, memory and inter-core bandwidths will also have to scale by orders of magnitude. Pin limitations, the energy cost of electrical signaling, and the non-scalability of chip-length global wires are significant bandwidth impediments. Recent developments in silicon nanophotonic technology have the potential to meet these off-and on-stack bandwidth requirements at acceptable power levels.Corona is a 3D many-core architecture that uses nanophotonic communication for both inter-core communication and off-stack communication to memory or I/O devices. Its peak floating-point performance is 10 teraflops. Dense wavelength division multiplexed optically connected memory modules provide 10 terabyte per second memory bandwidth. A photonic crossbar fully interconnects its 256 low-power multithreaded cores at 20 terabyte per second bandwidth. We have simulated a 1024 thread Corona system running synthetic benchmarks and scaled versions of the SPLASH-2 benchmark suite. We believe that in comparison with an electrically-connected many-core alternative that uses the same on-stack interconnect power, Corona can provide 2 to 6 times more performance on many memoryintensive workloads, while simultaneously reducing power.

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Section: Related Workmentioning

confidence: 99%

Corona: System Implications of Emerging Nanophotonic Technology

Vantrease

Schreiber

Monchiero

et al. 2008

2008 International Symposium on Computer Architecture

429

479

View full text Add to dashboard Cite

show abstract

“…Such TRNGs are a major component in cryptographic applications and can be found in commercial ICs. For example, the upcoming NIAGARA 2 processor from Sun couples one TRNG in each of its eight cores with cryptographic units to support secure generation of public and private keys [13]. We use TRNGs to define randomized chip IDs upon power-up, but such chip IDs can also be produced using onchip variation [17,18].…”

Section: On-chip True Random Number Generators (Trngs)mentioning

confidence: 99%

“…During the initial power-up, each chip generates a pair of private and public Random Chip Keys (RCK), which are burned into electricallyprogrammable fuses, e.g. the Electronic Fuse Unit (EFU) in Sun's NIAGARA 2 processor [13], to prevent multiple activation attempts. To activate a chip, the fab must establish a secure link with the holder of IP rights and transmit RCKPub for a chip that is being activated.…”

Section: Overview Of Proposed Techniquesmentioning

confidence: 99%

“…EPIC guarantees. EPIC's multi-layered protection requires two basic technology assumptions: (i) cryptographic security of RSA-like public-key crypto-systems, as well as (ii) good statistical properties of TRNGs or chip IDs [13,17,18], and their resilience to attacks (the randomness of RCK). Additionally, proper selection of CK in Section 6 ensures a limited number of good key combinations, and defeats brute-force and formal-methods attacks.…”

Section: Vulnerability Assessmentmentioning

confidence: 99%

“…RSA can also be turned off after activation (no power overhead) and does not affect critical paths (no delay overhead). Sun's NIAGARA 2 processor implements RSA in each of its 8 cores, with area overhead below 1% [13]. Impact on traditional design flows.…”

Section: Evaluation Of Proposed Techniquesmentioning

confidence: 99%

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EPIC: Ending Piracy of Integrated Circuits

Roy¹,

Koushanfar²

2008

2008 Design, Automation and Test in Europe

283

308

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As semiconductor manufacturing requires greater capital investments, the use of contract foundries has grown dramatically, increasing exposure to mask theft and unauthorized excess production. While only recently studied, IC piracy has now become a major challenge for the electronics and defense industries [6].We propose a novel comprehensive technique to end piracy of integrated circuits (EPIC). It requires that every chip be activated with an external key, which can only be generated by the holder of IP rights, and cannot be duplicated. EPIC is based on (i) automatically-generated chip IDs, (ii) a novel combinational locking algorithm, and (iii) innovative use of public-key cryptography. Our evaluation suggests that the overhead of EPIC on circuit delay and power is negligible, and the standard flows for verification

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