An 8-ns 256K ECL SRAM with CMOS memory array and battery backup capability

Tran, H.; Scott, David B.; Fung, P.K.; Havemann, R.H.; Eklund, Robert; Ham, T.E.; Haken, R.A.; Shah, A.H.

doi:10.1109/4.5922

Cited by 20 publications

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

64 K × 1 BiCMOS ECL RAM with cross‐coupled level conversion circuit

Shiomi

Takano

Honda

et al. 1992

Electron Comm Jpn Pt II

View full text Add to dashboard Cite

This paper considers the high‐speed, low‐power consumption BiCMOS ECL RAM and discusses the input buffer circuit, including the level conversion circuit which transforms the ECL level to MOS level. It is seen that the following circuit is the optimal from the viewpoints of the delay time and the power consumption. The address buffer circuit is composed of the ECL circuit and the emitter follower, the level conversion circuit is a CMOS cross‐coupled circuit, and the driver circuit is composed of the Bi‐nMOS driver. The high speed and low current dissipation performances are obtained with the delay time of 1.6 ns, current dissipation of 2.32 mA. The sense amplifier is constructed using ECL circuit with the constant‐current source with small dependencies on the temperature and the source voltage. A high speed is realized by producing the output from the wired‐OR of the emitter‐follower transistors of the blocks, with the time from the common data line to the output being 1.6 ns. Based on the obtained circuit structure, a 64 KX 1 bit BiCMOS ECL RAM is realized using the 1‐μm BiCMOS, with the access time of 7 ns and the power consumption of 800 mW [1].

show abstract

64 K × 1 BiCMOS ECL RAM with cross‐coupled level conversion circuit

Shiomi

Takano

Honda

et al. 1992

Electron Comm Jpn Pt II

View full text Add to dashboard Cite

show abstract

BICMOS technologies

Roche

1990

Trans Emerging Tel Tech

View full text Add to dashboard Cite

This paper describes why and how BICMOS technology will be one of the top three technology stars of the next decade. After a presentation of the specific advantages and drawback5 of Bipolar and CMOS technologies, the exploitation of characteristics of both components. realized on the same chip, is discussed. A brief description of BICMOS process architectures is given and the performances currently achieved are presented. Finally present and future applicarions are considered for Memories, Gate arrays, Telecommunications IC's, Analog IC's etc.

show abstract