An 82% energy-saving change-sensing flip-flop in 40nm CMOS for ultra-low power applications

Le, Van Loi; Li, Juhui; Chang, Alan; Kim, Tony T.

doi:10.1109/asscc.2017.8240250

Cited by 5 publications

(5 citation statements)

References 6 publications

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“…Further, it is essential to apply the CMOS process technology for many kinds of low-power digital basic building blocks, such as flip-flop (FF), memory, arithmetic logic unit, and so on [2]. Among them, the design of an FF, which represents the primary synchronous logic component of system-on-chip frameworks, has been widely studied [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. Figure 1 shows the circuit diagram of transmission-gate flip-flop (TGFF), which has been widely used in the field of digital systems [3].…”

Section: Introductionmentioning

confidence: 99%

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Design of a Dual Change-Sensing 24T Flip-Flop in 65 nm CMOS Technology for Ultra Low-Power System Chips

et al. 2022

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In this paper, a flip-flop (FF) that minimizes the transition of internal nodes by using a dual change-sensing scheme is discussed. Further, in order to reduce power consumption, a new technique to eliminate short-circuit currents is described. The proposed dual change-sensing FF (DCSFF) composed of 24T (T: number of transistors) has the lowest dynamic power consumption among conventional FFs, independent of the data activity ratio. According to the measured results with a 65 nm CMOS process, the power consumption of DCSFF is reduced by 98% and 32%, when the data activity is close to 0% and 100%, respectively, compared to that of conventional transmission gate FF. Further, compared to that of change-sensing FF, the power consumption of DCSFF is reduced by 26% when the data activity is close to 100%.

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Section: Introductionmentioning

confidence: 99%

“…(4) Small chip area: the chip size of the new FF should be smaller than that of conventional FFs. Even though various kinds of FFs to satisfy the requirements have been reported [8][9][10][11][12][13][14][15][16], a new scheme is proposed in this paper. The contents of this paper are as follows.…”

Section: Introductionmentioning

confidence: 99%

Design of a Dual Change-Sensing 24T Flip-Flop in 65 nm CMOS Technology for Ultra Low-Power System Chips

et al. 2022

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“…With the development of new process technology, the design method of FF continues to develop. Specific application requirements such as low voltage, low power, low cost or high performance also require new designs [ 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 ]. In this work, the FF design goal is a low voltage and low power consumption with a compact layout area design solution.…”

Section: Introductionmentioning

confidence: 99%

“…The CSFF (change sensing flip-flop) design includes an XOR logic in its master stage to check both input data with output Q as shown in Figure 1 e [ 18 , 19 ]. In this FF design, the input data are captured only when the discrepancy occurs.…”

Section: Introductionmentioning

confidence: 99%

Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design

Lin

Hong

et al. 2022

Sensors

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A low-voltage and low-power true single-phase flip-flop that minimum the total transistor count by using the pass transistor logic circuit scheme is proposed in this paper. Optimization measures lead to a new flip-flop design with better various performances such as speed, power, energy, and layout area. Based on post-layout simulation results using the TSMC CMOS 180 nm and 90 nm technologies, the proposed design achieves the conventional transmission-gate-based flip-flop design with a 53.6% reduction in power consumption and a 63.2% reduction in energy, with 12.5% input data switching activity. In order to further the performance parameters of the proposed design, a shift-register design has been realized. Experimental measurements at 0.5 V/0.5 MHz show that this proposed design reduces power consumption by 47.3% while achieving a layout area reduction of 30.5% compared to the conventional design.

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“…Based on the circuit techniques presented in this dissertation, there are further opportunities to further improve power, area efficiency, and performance in low-voltage VLSI systems such as IoT and wearable platforms. The proposed low-power CSFF [35]- [37] and ultra-low voltage LS [38] are planned to be employed in our future gesture recognition chip for further reducing power consumption and improving the performance of the overall system. Since the on-chip memory dominates the total power and area of the gesture recognition system [34], the use of the CSFF with the changesensing scheme can significantly minimize the dynamic power consumption of the whole system especially when there is no data activity.…”

Section: Proposed Outermost-edge-based Gesture Recognitionmentioning

confidence: 99%

Ultra-low power digital integrated circuit design

Le¹

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Pant for their support and advice on the presentation slides/posters before or during the conference. My special thanks again to IEEE JSSC Guest Editor, Prof. Chia-Hsiang Yang, for inviting my first work to IEEE JSSC Special Issue on A-SSCC 2017 and successfully handling the reviewing process. My special thanks also to IEEE TCAS-II Guest Editors, Prof. José M. de la Rosa and Prof. Mrityunjoy Chakraborty, for inviting my second work to TCAS-II Special Issue on ISCAS 2018 and successfully handling the reviewing process. I also would like to thank Prof. Zhou Jun, Dr. Yang Yongkui, and Goh Kim Seng for their technical support during the tape-out of my second test chip at A*STAR IME. I would also like to thank Prof. Dennis Sylvester for his useful advice during the meeting at NTU. I would also like to thank my QE committee members, Prof. See Kye Yak, Prof. Jong Ching Chuen, and Prof. Gwee Bah Hwee for their helpful advice and encouragements during my QE presentation. I would also like to thank my funding sources throughout my PhD career. First, to NXP Semiconductors and Economic Development Board Singapore for awarding me the Joint Industry Postgraduate Scholarship. I enormously appreciate for their incredibly generous support month after month through the years with monthly stipends and annual xii tuition fees. Without their assistance, I certainly would not have been able to take the path I did. Second, to the school of EEE, Nanyang Technological University. I am really thankful for the financial support for my first conference travel to South Korea, which was my first experience with a Solid-State Circuit conference. I would also like to thank A*STAR IME for their support for the tape-out of my second chip. I would also like to thank Isabella Lee Shiow Chyn, Xiaoyun Chen, Shirley Chua, and Elite Mao for their support and help over the financial issues during my time at NXP Semiconductors. I would also like to thank all of my colleagues in the low power VLSI design group for their help and support during my time at NTU. They are Dr. Yoo Taegeun, Dr. Do

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An 82% energy-saving change-sensing flip-flop in 40nm CMOS for ultra-low power applications

Cited by 5 publications

References 6 publications

Design of a Dual Change-Sensing 24T Flip-Flop in 65 nm CMOS Technology for Ultra Low-Power System Chips

Design of a Dual Change-Sensing 24T Flip-Flop in 65 nm CMOS Technology for Ultra Low-Power System Chips

Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design

Ultra-low power digital integrated circuit design

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