Design of a Dual Change-Sensing 24T Flip-Flop in 65 nm CMOS Technology for Ultra Low-Power System Chips

Abstract

In this paper, a flip-flop (FF) that minimizes the transition of internal nodes by using a dual change-sensing scheme is discussed. Further, in order to reduce power consumption, a new technique to eliminate short-circuit currents is described. The proposed dual change-sensing FF (DCSFF) composed of 24T (T: number of transistors) has the lowest dynamic power consumption among conventional FFs, independent of the data activity ratio. According to the measured results with a 65 nm CMOS process, the power consumption of DCSFF is reduced by 98% and 32%, when the data activity is close to 0% and 100%, respectively, compared to that of conventional transmission gate FF. Further, compared to that of change-sensing FF, the power consumption of DCSFF is reduced by 26% when the data activity is close to 100%.

Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design

“…With the development of new process technology, the design method of FF continues to develop. Specific application requirements such as low voltage, low power, low cost or high performance also require new designs [ 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 ]. In this work, the FF design goal is a low voltage and low power consumption with a compact layout area design solution.…”

“…This gives a performance edge in power over the conventional TGFF design when the switching activity is lower. However, some internal floating nodes already exist, and use up to 24 transistors [ 20 , 21 ].…”