An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS

Giannini, Vito; Nuzzo, Pierluigi; Chironi, V.; Basçhirotto, A.; Plas, G. Van der; Craninckx, Jan

doi:10.1109/isscc.2008.4523145

Cited by 133 publications

(74 citation statements)

References 4 publications

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“…4-21. It is seen that the SAR logic forms the dominant source of power consumption which agrees well with that of SAR ADCs with similar specification reported in [68], [9], [89], [90]. Post-layout simulation of the ADC including device noise was performed for the typical and worst PVT corners with near-Nyquist differential inputs and a sampling rate of 50 MS/s.…”

Section: Simulation Resultssupporting

confidence: 77%

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Harikumar¹

2016

Linköping Studies in Science and Technology. Dissertations

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Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these distributed WSNs are often low, ultra-low-power ADCs with low sampling rates are required. The advent of new wireless standards with ever-increasing data rates and bandwidth necessitates ADCs capable of meeting the demands. Wireless standards such as GSM, GPRS, LTE and WLAN require ADCs with several tens of MS/s speed and moderate resolution (8-10 bits). Since these ADCs are incorporated into battery-powered portable devices such as cellphones and tablets, low power consumption for the ADCs is essential.The first contribution is an ultra-low-power 8-bit, 1 kS/s successive approximation register (SAR) ADC that has been designed and fabricated in a 65-nm CMOS process. The target application for the ADC is an autonomously-powered soil-moisture sensor node. At V DD = 0.4 V, the ADC consumes 717 pW and achieves an FoM = 3.19 fJ/conv-step while meeting the targeted dynamic and static performance. The 8-bit ADC features a leakage-suppressed S/H circuit with boosted control voltage which achieves > 9-bit linearity. A binary-weighted capacitive array digital-to-analog converter (DAC) is employed with a very low, custom-designed unit capacitor of 1.9 fF. Consequently the area of the ADC and power consumption are reduced. The ADC achieves an ENOB of 7.81 bits at near-Nyquist input frequency. The core area occupied by the ADC is only 0.0126 mm 2 .The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and implemented in 65 nm CMOS aimed at communication applications. For medium-tohigh sampling rates, the DAC reference settling poses a speed bottleneck in chargeredistribution SAR ADCs due to the ringing associated with the parasitic inductances. Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip reference voltage buffers. The estimation of important design parameters of the buffer as well iv critical specifications such as power-supply sensitivity, output noise, offset, settling time and stability have been elaborated upon in this dissertation. The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages. The 10-bit SAR ADC utilizes split-array capacitive DACs to reduce area and power consumption. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the ...

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Section: Simulation Resultssupporting

confidence: 77%

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Harikumar¹

2016

Linköping Studies in Science and Technology. Dissertations

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“…One example is the noise-tolerant SAR ADC shown in Fig. 4 [15]. This design uses two offsetcalibrated fully dynamic comparators in parallel: one of these is designed for low power and consequently has fairly high noise (HN), whereas the other is optimized for low noise (LN) at a power penalty.…”

Section: Calibration Of Comparator Thresholdsmentioning

confidence: 99%

“…This design uses two offsetcalibrated fully dynamic comparators in parallel: one of these is designed for low power and consequently has fairly high noise (HN), whereas the other is optimized for low noise (LN) at a power penalty. In [15] the HN comparator is activated for the first eight SAR cycles, after which the LN comparator resolves two final cycles. By giving the final cycles 1b redundancy with respect to the first eight, the ADC can tolerate a fairly large r.m.s.…”

Section: Calibration Of Comparator Thresholdsmentioning

confidence: 99%

Digitally Assisted Analog to Digital Converters

Verbruggen¹

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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“…Since the RF front-end is usually the most power-hungry block in a node, its efficient implementation determines the choice of the technology in which the entire node is realized. In practice, this means the use of deep submicron CMOS processes, as these result in RF front-ends with the least amount of area and the greatest power efficiency [6][7][8], while also being favorable for the implementation of ADCs and digital circuitry [9][10][11]. As a result, for full integration, the CCIA must then be realized in the same technology.…”

Section: Introductionmentioning

confidence: 99%

Capacitively Coupled Chopper Instrumentation Amplifiers for Low-Voltage Applications

Fan

Makinwa

Huijsing³

2016

Analog Circuits and Signal Processing

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Chapter 6 has explored the use of a CCIA for high-side current sensing applications, where its wide CMVR and high power efficiency can be optimally leveraged. In Low-voltage (LV) applications, despite the much smaller CMVR, these advantages, together with the CCIA's high gain accuracy, are still quite useful. Therefore, in this chapter, a CCIA for LV applications, e.g., sensor readout, will be presented.This chapter starts with an introduction in which the targeted applications and requirements for the proposed CCIA are presented. Section 7.2 provides a brief overview of the state of the art, which is followed by the design of the proposed CCIA in Sect. 7.3. Section 7.4 discusses critical implementation details. Experimental results will be given in Sect. 7.5. Conclusions will be drawn in Sect. 7.6.

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An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS

Cited by 133 publications

References 4 publications

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Digitally Assisted Analog to Digital Converters

Capacitively Coupled Chopper Instrumentation Amplifiers for Low-Voltage Applications

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