An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection

Jalali, Mohammad Sadegh; Shivnaraine, Ravi; Sheikholeslami, Ali; Kibune, Masaya; Tamura, Hirotaka

doi:10.1109/cicc.2013.6658407

Cited by 10 publications

(12 citation statements)

References 7 publications

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“…Since the delay in resetting data phase is fixed (and small), no delay calibration circuit is needed. We will show that while the power consumption of this FD is similar to that of [13], its performance is improved by about 2 .…”

Section: Introductionmentioning

confidence: 88%

“…A clock-phase-selection (CPS) FD [13], takes advantage of this observation and by feeding the "correct" clock phase into the PD, eliminates the FD loop. This can be done by selecting the clock phase with a lower value of phase error on the edge of the data.…”

Section: B Frequency Detection Based On Clock Phase Adjustmentmentioning

confidence: 99%

“…Fig. 4(a) shows a half-rate linear CDR with a CPS FD, where the "correct" clock phase is found by selecting the higher of and if is positive and the lower of the two if is negative [13]. As shown in Fig.…”

Section: B Frequency Detection Based On Clock Phase Adjustmentmentioning

confidence: 99%

“…Although this solution leads to a wide capture range, it is slow. [13] and [14] periodically reset the the phase of the clock in order to limit the phase error. This enables the phase detector to deal with frequency offset, but it comes at the cost of limited improvement in capture range [13] and a complicated delay calibration circuitry [14].…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we propose a frequency detection scheme that aligns the data phase to the clock phase, and thereby improves the FD gain, capture range, and power consumption compared to previous work [13]. Since the delay in resetting data phase is fixed (and small), no delay calibration circuit is needed.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A Reference-Less Single-Loop Half-Rate Binary CDR

Jalali

Sheikholeslami

Kibune

et al. 2015

IEEE J. Solid-State Circuits

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This paper proposes a half-rate single-loop referenceless binary CDR that operates from 8.5 Gb/s to 12.1 Gb/s (36% capture range). The high capture range is made possible by adding a novel frequency detection mechanism which limits the magnitude of the phase error between the input data and the VCO clock. The proposed frequency detector produces three phases of the data, and feeds into the phase detector the data phase that minimizes the CDR phase error. This frequency detector, implemented within a 10 Gb/s CDR in Fujitsu's 65 nm CMOS, consumes 11 mW and improves the capture range by up to 6 when it is activated. He has been engaged in research and design of high-speed IO with CMOS.

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Section: Introductionmentioning

confidence: 88%

Section: B Frequency Detection Based On Clock Phase Adjustmentmentioning

confidence: 99%

Section: B Frequency Detection Based On Clock Phase Adjustmentmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Reference-Less Single-Loop Half-Rate Binary CDR

Jalali

Sheikholeslami

Kibune

et al. 2015

IEEE J. Solid-State Circuits

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A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

Wang

Chen

Yang

et al. 2023

Circuit Theory & Apps

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This paper reports a bang-bang clock and data recovery circuit (BBCDR) with an ultra-wide capture range. The circuit exhibits automatic frequency capture and phase locking over a wide 6-to-38 Gb/s range without using a frequency detector, allowed by a recently proposed deliberate-current-mismatch technique. Moreover, we accurately obtain an eight-phase clock through analog interpolation of quadrature signals over the whole wide frequency range by introducing a tunable capacitor array before an inverter-based phase interpolator. A 65-nm prototype of the developed BBCDR occupies an area of 0.07 mm 2 and attains a bit error rate of less than 10 À12 under a continuously variable input frequency, with a total power consumption of 24.6 mW for a 32-Gb/s non-return-zero input, thus leading to 0.769-pJ/bit energy efficiency.bang-bang clock and data recovery (BBCDR), current mismatch, frequency detector (FD), hybrid control circuit (HCC), phase interpolator (PI), ring oscillator (RO), R-2R digital-toanalog converter (DAC), switched-capacitor (SC) array, wide capture range

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Referenceless single‐loop CDR with a half‐rate linear PD and frequency acquisition technique

Kim

Chun

2020

Electron. lett.

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A referenceless single-loop clock and data recovery (CDR) circuit with a half-rate linear phase detector (PD) and an inherent frequency acquisition technique are introduced. Cycle-slip in the half-rate linear PD and its relationship with the frequency acquisition are described in detail. The single-loop CDR consists of a conventional phase-tracking loop and a frequency-tracking unit, referred to as the cycle-slip detector. The proposed CDR is fabricated in a 28 nm CMOS process and achieves a wide capture range of 2.6 Gb/s for a PRBS31 pattern. The RMS and peak-to-peak jitter of the recovered clock are 2.40 ps rms and 21.4 ps pp , respectively, at 8 Gb/s. The high frequency jitter tolerance is measured as 0.3 UI pp. The CDR occupies 0.105 mm 2 and consumes 26 mW at 8 Gb/s from a 1.0 V supply.

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An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection

Cited by 10 publications

References 7 publications

A Reference-Less Single-Loop Half-Rate Binary CDR

A Reference-Less Single-Loop Half-Rate Binary CDR

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

Referenceless single‐loop CDR with a half‐rate linear PD and frequency acquisition technique

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