No abstract

Abstract-A half-rate single-loop CDR with a new frequency detection scheme is introduced. The proposed frequency detector selects between the clock phases (I and Q) to reduce cycle slipping, hence improving lock time and capture range. This frequency detector, implemented within a 10Gb/s CDR in Fujitsu 65nm CMOS, consumes only 8mW, but improves the capture range by up to 3.6×. The measured capture range with the FD is from 8.675Gb/s to 11Gb/s.

Burst-mode clock and data recovery circuits (BMCDR) are widely used in passive optical networks (PON) [1] and as a replacement for conventional CDRs in clock-forwarding links to reduce power [2]. In PON, a single CDR performs the task of clock and data recovery for several burst sequences, each originating from a different source. As a result, the BMCDR is required to lock to an incoming data stream within tens of UIs (for example 40ns in GPON). Previous works use either injection locking [3,4] or gated VCO [5,6] to achieve this fast locking. In both cases, the control voltage of the CDR's VCO is generated by a reference PLL with a matching VCO to guarantee accurate frequency locking. However, any component mismatch between the two VCO's results in a frequency offset between the reference PLL frequency and the CDR's VCO frequency, and hence in a reduction of the CDR's tolerance for consecutive identical digits (CID). For example, [7] reports a frequency offset of over 20MHz (2000ppm) for 10Gb/s operation. We present a BMCDR that is based on phase interpolation (PI), eliminating the possibility of local frequency offset between the reference and recovered clock. We demonstrate 1 to 6Gb/s operation in 65nm CMOS with a locking time of less than 1UI.The principle of operation for the proposed PI-based BMCDR is illustrated in Fig. 8.7.1. Since the main function of a BMCDR is to align the rising edge of the clock with the data transition, we use the data to sample-and-hold (S/H) two quadrature clocks (CK I and CK Q ) with a pair of dual-edge-triggered S/H circuits. The samples of CK I and CK Q at a data transition, denoted by β and α respectively, are then used to interpolate between CK I and CK Q . This, as shown on Fig. 8.7.1, produces a recovered clock (CK REC ) with a rising edge that is aligned with the data transition. To demonstrate this analytically, assume sin(2πft) and -cos(2πft) represent CK I and CK Q respectively. A data transition at t = t 0 yields the PI coefficients α=CK Q (t 0 ) = -cos(2πft 0 ) and β=CK I (t 0 ) = sin(2πft 0 ). As a result, CK REC (t) = βCK Q (t) -αCK I (t) = sin(2πf(t-t 0 )) which is a clock whose zero crossing coincides with the data transition.In our implementation, CK I and CK Q are provided externally; however, in an integrated system CK I and CK Q may be provided from a PLL or be generated from the forwarded clock. In the case of using a received clock, there is no frequency mismatch between CK I /CK Q and the embedded clock in the data. When using a PLL, a small frequency offset may be present between CK I /CK Q and the input due to a frequency error in the PLL reference. For sufficient transition density, the PI's output phase is updated at every data transition, hence any frequency offset between data and the reference clock is tracked. Figure 8.7.2 shows the circuit implementation of the dual-edge triggered S/H. Dual-edge sampling is implemented by connecting the outputs of two S/Hs operating at opposite data edges. Each S/H is implemented as a master/slave configuration tr...

No abstract