An 8tb/s 1pj/b 0.8mm<sup>2</sup>/tb/s qdr inductive-coupling interface between 65nm cmos gpu and 0.1μm dram

Miura, Noriyuki; Kasuga, Kazutaka; Saito, Makoto; Kuroda, Tadahiro

doi:10.1109/isscc.2010.5433909

Cited by 24 publications

(18 citation statements)

References 3 publications

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“…In the prototype chip, we used a fine grained power grid in the layout of the analog domain to avoid the noise problem. The previous paper [24] reported a practical system, in which GPUs and DRAMs are connected with inductive coupling, and the feasibility of this system has been confirmed with real 3D ICs implementation in a 65-nm CMOS technology. Fig.…”

Section: Interference Issuementioning

confidence: 77%

“…A 1-Tbps inductive-coupling clock and data links have been developed by using 1,024 transceivers arranged with a pitch of 30 um [14]. Inductive coupling has already been used in various purposes, such as multicore processors [24] and dynamically reconfigurable processors [23]. Sections 3.4 and 4.2 describe the design and implementation of the inductors.…”

Section: Wireless 3d Interconnectionmentioning

confidence: 99%

“…This clock signal is needed for demultiplexing signals on the receiver side. In the test chip, T xclk is transferred using the inductive-coupling link, but it can be eliminated by using clock and data recovery (CDR) [24]. On the receiver side, the hysteresis comparator recovers the receiver clock Rxclk synchronized with the 8-Gbps received burst data (Rxdata).…”

Section: Interference Issuementioning

confidence: 99%

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3D NoC with Inductive-Coupling Links for Building-Block SiPs

Take

Matsutani

Sasaki

et al. 2014

IEEE Trans. Comput.

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A wireless 3D NoC architecture is described for building-block SiPs, in which the number of hardware components (or chips) in a package can be changed after chips have been fabricated. The architecture uses inductive-coupling links that can connect more than two examined dies without wire connections. Each chip has data transceivers for the uplink and downlink in order to communicate with its neighboring chips in the package. These chips form a vertical unidirectional ring network so as to fully exploit the flexibility of the wireless approach that enables us to add, remove, and swap the chips in the ring. To avoid protocol and structural deadlocks in the ring, we use bubble flow control, which does not rely on the conventional VC-based deadlock avoidance mechanism. In addition, we propose a bidirectional communication scheme to form a bidirectional ring network by using the inductive-coupling transceivers that can dynamically change the communication modes, such as TX, RX, and Idle modes. This paper illustrates the inductive-coupling transceiver circuits, which can carry high data transfer rates of up to 8 Gbps per channel, for the wireless 3D NoC. It also illustrates an implementation of a wireless 3D NoC that has on-chip routers and transceivers implemented with a 65 nm process in order to show the feasibility of our proposal. The vertical bubble flow control and conventional VC-based approach on the uni-and bidirectional ring networks are compared with the vertical broadcast bus in terms of throughput, hardware amount, and application performance using a full system multiprocessor simulator. The results show that the proposed bidirectional communication scheme efficiently improves application performance without adding any inductive-coupling transceivers. In addition, the proposed vertical bubble flow network outperforms the conventional VC-based approach by 7.9-12.5 percent with a 33.5 percent smaller router area for building-block SiPs connecting up to eight chips.

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Section: Interference Issuementioning

confidence: 77%

Section: Wireless 3d Interconnectionmentioning

confidence: 99%

Section: Interference Issuementioning

confidence: 99%

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3D NoC with Inductive-Coupling Links for Building-Block SiPs

Take

Matsutani

Sasaki

et al. 2014

IEEE Trans. Comput.

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“…The inductive-coupling provides a large degree of flexibility to build the target 3-D ICs, such as adding, re- moving, and swapping the chips in a package after the chip fabrication, like building blocks. Inductive-coupling is versatile and has been applied to various 3-D IC embedded systems, such as multi-core processors [8] and dynamically reconfigurable processors [9]. In addition, it has been applied to Network-on-Chips (NoCs) to extend the conventional 2-D NoC to 3-D [10].…”

Section: Introductionmentioning

confidence: 99%

Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs

Zhang

Matsutani

Take

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYWe propose low-power techniques for wireless threedimensional Network-on-Chips (wireless 3-D NoCs), in which the connections among routers on the same chip are wired while the routers on different chips are connected wirelessly using inductive-coupling. The proposed low-power techniques stop the clock and power supplies to the transmitter of the wireless vertical links only when their utilizations are higher than the threshold. Meanwhile, the whole wireless vertical link will be shut down when the utilization is lower than the threshold in order to reduce the power consumption of wireless 3-D NoCs. This paper uses an on-demand method, in which the dormant data transmitter or the whole vertical link will be activated as long as a flit comes. Full-system many-core simulations using power parameters derived from a real chip implementation show that the proposed low-power techniques reduce the power consumption by 23.4%-29.3%, while the performance overhead is less than 2.4%.

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“…The performance of the inductive coupling interconnect is comparable to TSVs in term of silicon usage, data rate, power consumption and ability to integrate multiple dies. Additional benefits are low cost, relaxed overlay alignment, high yield, and higher reliability compared to the physical counterparts [4]. Compared with the above interconnect technologies, capacitive coupling based interconnects allow better performance except it is only limited to the face-to-face configuration.…”

Section: Introductionmentioning

confidence: 99%

Design of self-biased fully differential receiver and crosstalk cancellation for capacitive coupled vertical interconnects in 3DICs

Aung

Lim²,

Yoshikawa

et al. 2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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Interconnect density in traditional capacitive coupling electrodes array is limited by capacitive crosstalk between electrodes. In this work, we propose an array structure where single-ended and differential pair electrodes (designed in the common-centroid structure) are alternatively placed horizontally and vertically. The proposed structure not only cancels out the crosstalk noise but also reduces the spacing requirement between electrodes. A novel self-biased fully differential receiver suppresses the common-mode coupled crosstalk in the differential electrodes. The receiver provides CMRR of 25dB and can recover wide band (10 kHz ~ 1 GHz) signals with 32dB gain. It consumes 25 µW at 1 GHz. It is designed and simulated in a 1.5V 0.13µm CMOS technology.I.

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An 8tb/s 1pj/b 0.8mm²/tb/s qdr inductive-coupling interface between 65nm cmos gpu and 0.1μm dram

Cited by 24 publications

References 3 publications

3D NoC with Inductive-Coupling Links for Building-Block SiPs

3D NoC with Inductive-Coupling Links for Building-Block SiPs

Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs

Design of self-biased fully differential receiver and crosstalk cancellation for capacitive coupled vertical interconnects in 3DICs

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An 8tb/s 1pj/b 0.8mm2/tb/s qdr inductive-coupling interface between 65nm cmos gpu and 0.1μm dram

Cited by 24 publications

References 3 publications

3D NoC with Inductive-Coupling Links for Building-Block SiPs

3D NoC with Inductive-Coupling Links for Building-Block SiPs

Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs

Design of self-biased fully differential receiver and crosstalk cancellation for capacitive coupled vertical interconnects in 3DICs

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An 8tb/s 1pj/b 0.8mm²/tb/s qdr inductive-coupling interface between 65nm cmos gpu and 0.1μm dram