An Academic RISC-V Silicon Implementation Based on Open-Source Components

Abella, Jaume; Bulla, Calvin; Cabo, Guillem; Cazorla, Francisco J.; Cristal, Adrián; Doblas, Max; Figueras, Roger; González, Alberto; Hernández, Carles; Hernández, César; Jiménez, Víctor; Kosmidis, Leonidas; Kostalabros, Vatistas; Langarita, Rubén; Leyva, Neiel; López-Paradís, Guillem; Marimon, Joan; Martı́nez, Ricardo; Mendoza, Jonnatan; Moll, Francesc; Moreteo, Miquel; Pavón, Julián; Ramiez, Cristobal; García-Ramírez, Mario Alberto; Rojas, Carlos; Rubio, Antonio; Ruiz, Abraham; Sönmez, Nehir; Soria, Victor; Terés, Lluís; Ünsal, Osman; Valero, Mateo; Vargas, Ivan; Villa, Luis

doi:10.1109/dcis51330.2020.9268664

Cited by 9 publications

(7 citation statements)

References 4 publications

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“…Hence, we decided to make use of the DDR3 controller and DDR3 Memory IPs available on a Xilinx KC705 Field-Programmable Gate Array (FPGA) board as a backup option to access main memory. This solution was used in the preDRAC chip [5].…”

Section: Chip Architecturementioning

confidence: 99%

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology

Cabo

Candon

Carril

et al. 2022

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)

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This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The DVINO processor includes an internally developed two-lane vector processor unit as well as a Phase Locked Loop (PLL) and an Analog-to-Digital Converter (ADC). The paper summarizes the design from architectural as well as logic synthesis and physical design in CMOS 65nm technology.

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Section: Chip Architecturementioning

confidence: 99%

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology

Cabo

Candon

Carril

et al. 2022

2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS)

Self Cite

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“…Considering the reference example depicted in Figure 1a, we can evaluate the IP between u = [7,5] and v = [4,2] via binary segmentation employing a single integer multiplication. Specifically, we represent each element of the input vector with a bitwidth equal to the clustering width defined in Equation (4) (i.e., 7-bit), and we revert the order of the elements belonging to v (blue).…”

Section: Inner Product Of Two Vectors Via Binary Segmentationmentioning

confidence: 99%

“…Then, we recover w from the output of the integer multiplication between U cw and V cw . An example of LC between two vectors u = [3, 1, 2] and v = [1,2] is shown in Figure 1b. First, the bitwidth of each element belonging to u and v is represented as a 5-bit number, according to Equation (7) (blue).…”

Section: Convolution Of Two Vectors Via Binary Segmentationmentioning

confidence: 99%

“…As detailed in Section 3.2, the main bottleneck of performing the LC kernel with binary segmentation relates with the post-processing phase, since the result of every convolution has to be extracted and accumulated into the output vector. The proposed solution exploits bs.lc.l bs.lc.h ova[0] ova [1] ova [2] ova [3] ova [4] ova [5] ova [6] Figure 6: Improved overlap-add using BiSon-e. Different colors represent different outer loop iterations.…”

Section: Fused Overlap-addmentioning

confidence: 99%

“…We integrated BiSon-e into the DRAC SoC design [2], using the Cadence tool flow (Genus/Innovus), to obtain the layout and main performance metrics of the overall microarchitecture. We implemented the design in two different technologies, namely TSMC 65nm bulk CMOS and GlobalFoundries 22 nm FDSOI.…”

Section: Area and Power Analysismentioning

confidence: 99%

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BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge

Reggiani

Lazo

Figueras

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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Linear algebra computational kernels based on byte and sub-byte integer data formats are at the base of many classes of applications, ranging from Deep Learning to Pattern Matching. Porting the computation of these applications from cloud to edge and mobile devices would enable significant improvements in terms of security, safety, and energy efficiency. However, despite their low memory and energy demands, their intrinsically high computational intensity makes the execution of these workloads challenging on highly resource-constrained devices. In this paper, we present BiSon-e, a novel RISC-V based architecture that accelerates linear algebra kernels based on narrow integer computations on edge processors by performing Single Instruction Multiple Data (SIMD) operations on off-the-shelf scalar Functional Units (FUs). Our novel architecture is built upon the binary segmentation technique, which allows to significantly reduce the memory footprint and the arithmetic intensity of linear algebra kernels requiring narrow data sizes. We integrate BiSon-e into a complete System-on-Chip (SoC) based on RISC-V, synthesized and Place&Routed in 65nm and 22nm technologies, introducing a negligible 0.07% area overhead with respect to the baseline architecture. Our experimental evaluation shows that, when computing the Convolution and Fully-Connected layers of the AlexNet and VGG-16 Convolutional Neural Networks (CNNs) with 8-, 4-, and 2-bit, our solution gains up to 5.6×, 13.9× and 24× in execution time compared to the scalar implementation of a single RISC-V core, and improves the energy efficiency of string matching tasks by 5× when compared to a RISC-V-based Vector Processing Unit (VPU).

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RISC-V for Genome Data Analysis: Opportunities and Challenges

López-Villellas,

Pineda-Sánchez,

Badouh

et al. 2023

2023 38th Conference on Design of Circuits and Integrated Systems (DCIS)

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The RISC-V ISA has gained significant momentum in High-Performance Computing (HPC) research and market due to its open-source nature, fostering collaborative research and innovation. The ever-growing RISC-V-based hardware/software ecosystem has made it an attractive option for HPC application development and production. Within the field of biomedical research, genome data analysis has emerged as a crucial step towards personalized medicine, demanding substantial computational resources and more efficient tools.This paper presents a benchmark suite of genome analysis kernels ported to RISC-V and their evaluation on modern RISC-V systems. Our work evaluates the RISC-V toolchain's maturity and the software/hardware ecosystem's readiness for its adoption for genome data analysis. This study aims to provide valuable guidance for researchers and practitioners interested in adopting RISC-V for genome analysis, and provides feedback to the RISC-V community on the challenges that need to be addressed for RISC-V to become an efficient HPC platform.

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An Academic RISC-V Silicon Implementation Based on Open-Source Components

Cited by 9 publications

References 4 publications

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology

BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge

RISC-V for Genome Data Analysis: Opportunities and Challenges

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