An adaptive analog noise-predictive decision-feedback equalizer

Le, M.Q.; Hurst, P.J.; Keane, John

doi:10.1109/4.982416

Cited by 33 publications

(10 citation statements)

References 13 publications

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“…From (5), the error, , is equal to zero if and only if the following identity holds: for all (6) Laplace transformation on both sides of (6) and appropriate manipulation lead to the following identity:…”

Section: First-order Adaptive Equalizermentioning

confidence: 97%

Convergence analysis of the cascade second-order adaptive line equalizer

Yoo

Han

Yoon

2006

IEEE Trans. Circuits Syst. II

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The high-speed data transmission on a twisted pair cable suffers from frequency-dependent loss that causes significant inter-symbol interference. Although a first-order adaptive equalizer based on pole-zero cancellation is sufficient to compensate the limited bandwidth for relatively low data rate, a higher order equalizer is necessary for higher data rate. This brief proposes a cascade second-order adaptive equalizer structure and provides its convergence analysis.

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Section: First-order Adaptive Equalizermentioning

confidence: 97%

Convergence analysis of the cascade second-order adaptive line equalizer

Yoo

Han

Yoon

2006

IEEE Trans. Circuits Syst. II

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“…This type of equalization is referred to as forward equalization, while the high-pass front-end receiver is called forward equalizer (FE). Since FEs remove the effect of ISI by restoring the original shape of the received waveform through enhancing the speed of transitions (high-pass response), they do not require any knowledge of the previously received bits in the data stream in order to remove ISI [7]- [10]. This makes them more attractive for purely analog implementation techniques with minimal area/power/cost overhead and without requiring any phase-locked loop (PLL) or CDR circuits.…”

Section: Equalizer Systemmentioning

confidence: 98%

A Low-Voltage Low-Power CMOS Analog Adaptive Equalizer for UTP-5 Cables

Fayed

Ismail

2008

IEEE Trans. Circuits Syst. I

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An analog adaptive equalizer based on a feed-forward architecture is implemented in 0.18-m digital CMOS process. The equalizer is implemented with only digital core devices and operates at 125 Mbps over Unshielded-Twisted-Pair Category-5 cable of up to 100 m. Novel low-power circuit and system techniques resulted in 3.7-mW total power consumption and supply voltage operation as low as 1.6 V. The maximum peak-to-peak jitter at the output of the equalizer (including the transmit path driver) under all cable length is 0.33 UI. The total area of the equalizer is 27738 m 2 .

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“…6(a) shows the architecture of the filter as a neural network adapting with anti-Hebbian learning rules. If the inputs to the neuron are drawn from a tapped-delay line (such as the barrel-shifter analog line described in [8]), then the neuron implements an adaptive FIR filter. Because input offsets in the forward-path multipliers translate into nonzero-mean inputs and degrade the performance of the filter [4], we use a bias synapse w 0 with a constant input to compensate for the aggregated value of all the input offsets in the neuron [1].…”

Section: A Linear Filter With Lms Adaptationmentioning

confidence: 99%

Adaptive signal processing in mixed-signal VLSI with anti-Hebbian learning

Figueroa

Matamala

Carvajal

et al. 2006

IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06)

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We describe analog and mixed-signal primitives for implementing adaptive signal-processing algorithms in VLSI based on anti-Hebbian learning. Both on-chip calibration techniques and the adaptive nature of the algorithms allow us to compensate for the effects of device mismatch. We use our primitives to implement a linear filter trained with the Least-Mean Squares (LMS) algorithm and an adaptive decorrelation network that improves the convergence of LMS. When applied to an adaptive Code-Division MultipleAccess (CDMA) despreading application, our system, without the need for power control, achieves more than 100x improvement in the bit-error ratio in the presence of high interference between users. Our 64-tap linear filter uses 0.25mm 2 of die area and dissipates 200μW in a 0.35μm CMOS process.

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An adaptive analog noise-predictive decision-feedback equalizer

Cited by 33 publications

References 13 publications

Convergence analysis of the cascade second-order adaptive line equalizer

Convergence analysis of the cascade second-order adaptive line equalizer

A Low-Voltage Low-Power CMOS Analog Adaptive Equalizer for UTP-5 Cables

Adaptive signal processing in mixed-signal VLSI with anti-Hebbian learning

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