An adaptive clocking control circuit with 7.5% frequency gain for SPARC processors

Hashimoto, Takahiro; Kawabe, Yojiro; Kara, Michiharu; Kakimura, Yasushi; Tajiri, K.; Shirota, S; Nishiyama, Ryuichi; Sakuraï, H.; Okano, Hiroshi; Tomita, Yoshihiro; Satoh, Sugio; Yamashita, Hideo

doi:10.23919/vlsit.2017.7998133

Cited by 1 publication

(2 citation statements)

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“…Combined with a critical path monitoring mechanism, researchers achieve voltage scaling when the critical path is not excited while using the available timing margin as a guardband mechanism. Another work utilizes a unary coding scheme to enable the PLL to quickly adapt to the required clock changes in real time [19]. This approach can be applied on a single core clock to enable its dynamic frequency change without imposing significant delays.…”

Section: Previous Researchmentioning

confidence: 99%

“…We adopt this approach as we acknowledge the need for a robust real time clock scaling mechanism. In contrast with [19] and [20] which manage to change the clock frequency for up to 7.5% of the core clock speed, we require much higher adaptation values. For that reason we do not change the clock frequency directly, instead we pre-generate the number of PLLs required and we proceed in selecting the appropriate candidate each time.…”

Section: Dynamic Clock Scaling Mechanismmentioning

confidence: 99%

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Frequency Scaling for High Performance of Low-End Pipelined Processors

Tziouvaras¹,

Dimitriou²,

Dossis³

et al. 2021

Adv. sci. technol. eng. syst. j.

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In the Internet of Things era it is expected that low-end processor domination of the embedded market will be further reaffirmed. Then, a question will arise, on whether it is possible to enhance performance of such processors without the cost of high-end architectures. In this work we propose a better-than-worst-case (BTWC) methodology which enables the processor pipeline to operate at higher clock frequencies compared to the worst-case design approach. We employ a novel timing analysis technique, which calculates the timing requirements of individual processor instructions statically, while also considering the dynamic instruction flow in the processor pipeline. Therefore, using an appropriate circuit that we designed within this work, we are able to selectively increase clock frequency, according to the timing needs of the instructions currently occupying the processor pipeline. In this way, the error-free instruction execution is preserved without requiring any error-correction hardware. We evaluate the proposed methodology on two different RiscV Rocket core implementations. Results with the SPEC 2017 CPU benchmark suite demonstrate a 12% to 76% increase on the BTWC design performance compared to the baseline architectures, depending on the appearance rate of instructions with strict timing requirements. We also observe a 4% to 37% increase on power consumption due to the operation of the pipeline at higher clock frequencies. Nevertheless, the performance increase is up to nine times larger than the power consumption increase for each case.

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Section: Previous Researchmentioning

confidence: 99%

Section: Dynamic Clock Scaling Mechanismmentioning

confidence: 99%