An Adaptive Digital Fuzzy Architecture forApplication‐Specific Integrated Circuits

Evmorfopoulos, Nestor; Avaritsiotis, J.N.

doi:10.1080/08827510214374

Cited by 8 publications

(6 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For processing the output, four parallel maximum units are used. The numerator N and denominator D is calculated using equation (8) and (9), respectively.…”

Section: B Inference Decisionmentioning

confidence: 99%

“…J.M. Jou et al [7], R. d 'Amore [8] and N. E. Evmorfopoulong et al [9] have proposed different architecture for the fuzzy inference processor.…”

Section: Introductionmentioning

confidence: 99%

“…Many variations [1][2][3][4][5][6][7][8][9][10][11][12][13][14] have been proposed to improve the inferencing performance. The speed bottleneck of these fuzzy inference processors lies in the calculation of the matching degree.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

FPGA Based Pipelined Parallel Architecture for Fuzzy Logic Controller

Kapse¹,

Jharia²,

Thakur³

2012

IJMECS

View full text Add to dashboard Cite

This paper presents a high-speed VLSI fuzzy inference processor for the real-time applications using trapezoid-shaped membership functions. Analysis shows that the matching degree between two trapezoid-shaped membership functions can be obtained without traversing all the elements in the universal disclosure set of all possible conditions. A FPGA based pipelined parallel VLSI architecture has been proposed to take advantage of this basic idea, implemented on CycloneII-EP2C70F896C8. The controller is capable of processing fuzzified input. The proposed controller is designed for 2-input 1output with maximum clock rate is 12.96 MHz and 275.33 MHz for 16 and 8 rules respectively. Thus, the inference speed is 0.81 and 34.41 MFLIPS for 16 and 8 rules, respectively.

show abstract

“…For processing the output, four parallel maximum units are used. The numerator N and denominator D is calculated using equation (8) and (9), respectively.…”

Section: B Inference Decisionmentioning

confidence: 99%

“…J.M. Jou et al [7], R. d 'Amore [8] and N. E. Evmorfopoulong et al [9] have proposed different architecture for the fuzzy inference processor.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

FPGA Based Pipelined Parallel Architecture for Fuzzy Logic Controller

Kapse¹,

Jharia²,

Thakur³

2012

IJMECS

View full text Add to dashboard Cite

show abstract

“…A bit scalable architecture of fuzzy processors is proposed, this architecture is suited for automatic synthesis of digital fuzzy controller by R. d 'Amore [15]. N. E. Evmorfopoulong et al [16] have proposed different architecture for the fuzzy inference processor. A significant improvement is reducing power and reducing redundancy has been obtained in this structure.…”

Section: Introductionmentioning

confidence: 99%

Center of Sums based Defuzzifier Unit VLSI Architecture

Murshid¹

2023

Tikrit J. Pure Sci.

View full text Add to dashboard Cite

Defuzzification is a process of getting a crisp value from the fuzzy data. Since the fuzzy data cannot be used directly for the real time applications, therefore it has to be converted into a crisp value. In designing the defuzzification unit in this work, the center of sums has been used, because of its computationally efficient nature. The Center of Sums (COS) is faster than many defuzzification method and the method is not restricted to symmetric membership function is simple and is being generally used in comparison to more complex Center of gravity (also called Center of area or Centroid method) defuzzification method. The proposed architecture has been modeled in VHDL and implemented in XILINX and Spartan field programmable gate arrays (FPGA). The proposed architecture is more efficient in area (the area of implementation of VLSI Architecture) and the speed of operation in comparison to a more complex architecture used for the Center of gravity. The functional analysis has revealed that the proposed architecture is implementing COS based defuzzifier efficiently and accurately.

show abstract

“…J.M. Jou et al [10], R. d 'Amore [11] and N. E. Evmorfopoulong et al [12] have proposed different architecture for the fuzzy inference processor. A significant improvement is reducing power and reducing redundancy has been obtained in these structures.…”

Section: Introductionmentioning

confidence: 99%

Architectural design of fuzzy inference processor using triangular-shaped membership function

Murshid

Loan

2011

2011 IEEE Conference on Open Systems

View full text Add to dashboard Cite

The hardware design of a fuzzy processor is always intended to improve its inference performance for real time applications or to reduce the overall cost. The applications of fuzzy logic in various fields have always suffered from a major problem of low speed of operation. The calculation of matching degree always needs very high latency and limits the overall inference performance. In this paper, a novel architecture for calculating the matching between two triangular-shaped membership functions has been proposed. The VHDL implementation of the proposed architecture has been performed. The proposed architecture is more efficient in area and the speed of operation in comparison to a more complex architecture used for the trapezoid-shaped membership function. The proposed architecture has been implemented in a Xilinx Field Programmable Gate Array (FPGA). Further, from the proposed architecture, matching of other type of membership functions can also be obtained easily.

show abstract

An Adaptive Digital Fuzzy Architecture forApplication‐Specific Integrated Circuits

Cited by 8 publications

References 21 publications

FPGA Based Pipelined Parallel Architecture for Fuzzy Logic Controller

FPGA Based Pipelined Parallel Architecture for Fuzzy Logic Controller

Center of Sums based Defuzzifier Unit VLSI Architecture

Architectural design of fuzzy inference processor using triangular-shaped membership function

Contact Info

Product

Resources

About