Architectural design of fuzzy inference processor using triangular-shaped membership function

Abstract

The hardware design of a fuzzy processor is always intended to improve its inference performance for real time applications or to reduce the overall cost. The applications of fuzzy logic in various fields have always suffered from a major problem of low speed of operation. The calculation of matching degree always needs very high latency and limits the overall inference performance. In this paper, a novel architecture for calculating the matching between two triangular-shaped membership functions has been proposed. The VHDL implementation of the proposed architecture has been performed. The proposed architecture is more efficient in area and the speed of operation in comparison to a more complex architecture used for the trapezoid-shaped membership function. The proposed architecture has been implemented in a Xilinx Field Programmable Gate Array (FPGA). Further, from the proposed architecture, matching of other type of membership functions can also be obtained easily.

An evaluation method of contribution rate based on fuzzy Bayesian networks for equipment system-of-systems architecture

“…1, the flow chart of transformation from the T-S fuzzy fault tree to FBN is presented. Consider various failure states of nodes, the fuzzy numbers [28] distributed on [0,1] are used to describe the polymorphism of node failure states, the language value set {no failure, slight failure, complete failure} is used to describe the node failure states, and the fuzzy numbers 0, 0.5, 1 are used to describe the language values, the number of failure states is 3. Assume that the variables of FBN are and T , which respectively represent the root nodes, the intermediate nodes, and leaf nodes.…”