An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement

Abstract

Abstract-An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20", 30", 40" FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a 0.13 μm process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.Index Terms-Adaptive equalizer, USB 3.0 high-speed receiver, jitter measurement

Development of WDM System in Optical Amplifiers by Manipulating Fiber Length and Bandwidth for Telecommunication System

“…The small slope of the eye diagram indicates that the jitter is not significant effect. The value of noise which can be tolerated is rather high, it means the small value of noise occurs hence the small distortion occurs [22]. The formed eye diagram is not surprising where the losses occur, much power is wasted and the value of noise allowed is still small.…”