An adaptive low-power transmission scheme for on-chip networks

Worm, F.; Ienne, Paolo; Thiran, Patrick; Micheli, Giovanni De

doi:10.1145/581199.581221

Cited by 76 publications

(17 citation statements)

References 18 publications

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“…A first extension of Fig. 2(a) in this direction is discussed in [40]. To reduce the energy consumed per bit, we apply DVSS by controlling dynamically the driver swing and the corresponding receiver threshold.…”

Section: Dvss For On-chip Interconnectsmentioning

confidence: 99%

A robust self-calibrating transmission scheme for on-chip networks

Worm

Ienne

Thiran

et al. 2005

IEEE Trans. VLSI Syst.

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Abstract-Systems-on-Chip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are increasingly related to correct, reliable, and robust operation. We believe that in the future most SoCs will be assembled by using large-scale macro-cells and interconnected by means of on-chip networks. In this paper, we examine some physical properties of on-chip interconnect busses, with the goal of achieving fast, reliable, and low-energy communication. These objectives are reached by dynamically scaling down the voltage swing, while ensuring data integrity-in spite of the decreased signal to noise ratio-by means of encoding and retransmission schemes. In particular, we describe a closed-loop voltage swing controller that samples the error retransmission rate to determine the operational voltage swing. We present a control policy which achieves our goals with minimal complexity; such simplicity is demonstrated by implementing the policy in a synthesizable controller. Such a controller is an embodiment of a self-calibrating circuit that compensates for significant manufacturing parameter deviations and environmental variations. Experimental results show that energy savings amount up to 42%, while at the same time meeting performance requirements.Index Terms-Electrical parameter variations, interconnect for networks-on-chip, low-power systems-on-chip (SoC), self-calibrating designs, VLSI design methodology.

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Section: Dvss For On-chip Interconnectsmentioning

confidence: 99%

A robust self-calibrating transmission scheme for on-chip networks

Worm

Ienne

Thiran

et al. 2005

IEEE Trans. VLSI Syst.

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“…Shang et al [7] developed a history-based DVS policy which adjusts operating voltage and clock frequency of a link according to the utilization of link and input buffer. Worm et al [8] proposed an adaptive low-power transmission scheme for onchip networks. They minimized the energy required for reliable communication, while satisfying QoS constraints.…”

Section: Related Workmentioning

confidence: 99%

A variable frequency link for a power-aware network-on-chip (NoC)

Lee

Bagherzadeh

2009

Integration

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“…14 The issue most relevant to achieving self-calibration is the availability of a reliable error model as a function of the voltage swing and the transmission frequency.…”

Section: Challenges Of Self-calibrationmentioning

confidence: 99%

On-chip self-calibrating communication techniques robust to electrical parameter variations

Worm

Ienne

Thiran

et al. 2004

IEEE Des. Test. Comput.

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RECENT SILICON TECHNOLOGIES used for SoCs are increasingly different from original CMOS, which was an almost ideal digital technology. Second-order effects of different sorts, such as capacitive or inductive crosstalk, have become more critical because of a wealth of physical phenomena, including 3D and quantum effects. Similarly, ever-decreasing geometries are widening the spread of electrical parameters linked to imprecision in the manufacturing process. All these factors contribute significantly to design process complexity. Without a dramatic, unforeseen change in circuit and manufacturing technology, this situation can only get worse.The adopted design methodologies have always been based on worst-case design approaches. Gate and interconnect delays are a typical example. Circuits clock registers only when data is sure to be stable, and designers use worst-case analysis-as determined, for example, by static timing analyzers-to achieve this timing estimate. Designers simply model all sources of deviation from the nominal situation and total them to determine the most conservative estimate of the incurred delay.Observed trends in worst-case analysis for current design methodologies could invalidate the benefits of faster, scaled-down semiconductor technologies. As a result, large capital investments in deep-submicron silicon fabrication might not return competitive chips. Worst-case design will show diminishing returns in speed as designers scale down devices and supply voltages. The complex interaction of several physical factors will become increasingly harder to model accurately, pushing designers toward ever more conservative assumptions. Although some research aims to improve the accuracy of worst-case static timing estimations, 1 a more radical approach is needed. Otherwise, there will be a heavy price to pay-mostly in terms of energy consumption-even as power savings becomes a primary goal in many SoC applications. Figure 1 illustrates the point with a simple qualitative example. Recall that accurate knowledge of the delay and voltage relation is key for many optimization techniques, such as transistor sizing and dynamic voltage scaling. The nominal relation between delay and supply voltage is modified by several physical phenomena, whose cumulative effects constitute a worst-case relation. Therefore, at a given supply voltage, V DD , a designer will assume the most conservative delay-that is, that the operating point is not, for instance, A but B-and implement the design accordingly. However, at a particular instant, the device is likely to be operating under far more favorable conditions-for instance, with a lower delay indicated by operating point C. This implies a waste of energy because operation at reduced voltage V DD ′ (B′) On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter VariationsEditor's note: Dynamic self-calibration holds the promise of overcoming conservative worstcase design techniques needed to combat deep-submicron process and operating variations. This ...

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An adaptive low-power transmission scheme for on-chip networks

Cited by 76 publications

References 18 publications

A robust self-calibrating transmission scheme for on-chip networks

A robust self-calibrating transmission scheme for on-chip networks

A variable frequency link for a power-aware network-on-chip (NoC)

On-chip self-calibrating communication techniques robust to electrical parameter variations

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