A variable frequency link for a power-aware network-on-chip (NoC)

Lee, Seung Eun; Bagherzadeh, Nader

doi:10.1016/j.vlsi.2009.01.002

Cited by 47 publications

(16 citation statements)

References 17 publications

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“…An adaptive routing strategy that intelligently uses a subset of links for communication was proposed, thereby facilitating DLS for minimizing energy consumption. Lee et al [13] presented a variable frequency link for a power-aware interconnection network using the clock boosting mechanism, and applied a dynamic frequency scaling (DFS) to a 2-D NoC in order to judiciously adjust link frequency based on link utilization. However, since it is difficult to control the frequency and supply voltage of the tranceiver and receiver used in the inductive coupling, traditional techniques around DVFS are difficult to be used.…”

Section: Related Workmentioning

confidence: 99%

Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs

Zhang

Matsutani

Take

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYWe propose low-power techniques for wireless threedimensional Network-on-Chips (wireless 3-D NoCs), in which the connections among routers on the same chip are wired while the routers on different chips are connected wirelessly using inductive-coupling. The proposed low-power techniques stop the clock and power supplies to the transmitter of the wireless vertical links only when their utilizations are higher than the threshold. Meanwhile, the whole wireless vertical link will be shut down when the utilization is lower than the threshold in order to reduce the power consumption of wireless 3-D NoCs. This paper uses an on-demand method, in which the dormant data transmitter or the whole vertical link will be activated as long as a flit comes. Full-system many-core simulations using power parameters derived from a real chip implementation show that the proposed low-power techniques reduce the power consumption by 23.4%-29.3%, while the performance overhead is less than 2.4%.

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Section: Related Workmentioning

confidence: 99%

Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs

Zhang

Matsutani

Take

et al. 2013

IEICE Trans. Inf. & Syst.

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“…Dynamic Voltage and Frequency Scaling (DVFS) and turning off unused links are among the most efficient techniques that can take advantage of the variation in traffic to reduce power [17,1,10]. Static knowledge of the traffic patterns obtained by compiler analysis was also used to optimize the frequency/voltage scaling of the individual interconnection links in the network [11].…”

Section: Related Workmentioning

confidence: 99%

Power-aware Manhattan Routing on Chip Multiprocessors

Benoît

Melhem

Renaud-Goud

et al. 2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium

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Abstract:We investigate the routing of communications in chip multiprocessors (CMPs). The goal is to find a valid routing in the sense that the amount of data routed between two neighboring cores does not exceed the maximum link bandwidth while the power dissipated by communications is minimized. Our position is at the system level: we assume that several applications, described as task graphs, are executed on a CMP, and each task is already mapped to a core. Therefore, we consider a set of communications that have to be routed between the cores of the CMP. We consider a classical model, where the power consumed by a communication link is the sum of a static part and a dynamic part, with the dynamic part depending on the frequency of the link. This frequency is scalable and it is proportional to the throughput of the link. The most natural and widely used algorithm to handle all these communications is XY routing: for each communication, data is first forwarded horizontally, and then vertically, from source to destination. However, if it is allowed to use all Manhattan paths between the source and the destination, the consumed power can be reduced dramatically. Moreover, some solutions may be found while none existed with the XY routing. In this paper, we compare XY routing and Manhattan routing, both from a theoretical and from a practical point of view. We consider two variants of Manhattan routing: in single-path routing, only one path can be used for each communication, while multi-paths routing allows to split a communication between different routes. We establish the NP-completeness of the problem of finding a Manhattan routing that minimizes the dissipated power, we exhibit the minimum upper bound of the ratio power consumed by an XY routing over power consumed by a Manhattan routing, and finally we perform simulations to assess the performance of Manhattan routing heuristics that we designed.Key-words: routing; chip multiprocessor; energy; power; Manhattan; singlepath; multi-paths; complexity. inria-00629804, version 2 -6 Oct 2011Routage de Manhattan minimisant la puissance dissipée sur des processeurs multi-coeurs

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“…Previous work in [11,12,21] has specifically focused on link latency/power. Mishra et al [17] enabled DVFS on NoC routers to reduce the network power consumption.…”

Section: Related Workmentioning

confidence: 99%

“…Dynamic Voltage and Frequency Scaling (DVFS) is an effective technique for reducing network energy dissipation [12,17,21]. The key idea behind network DVFS is to dynamically scale the supply voltage of the routers and links to provide justenough circuit speed to process the traffic workload.…”

Section: Introductionmentioning

confidence: 99%

Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems

Yin

Zhou

Holey

et al. 2012

Proceedings of the 2012 ACM/IEEE International Symposium on Low Power Electronics and Design

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Network-on-Chips (NoCs) in heterogeneous systems containing both CPU and GPU cores must be designed to satisfy the performance requirements of both latency-sensitive CPU traffic and throughput-intensive GPU traffic. DVFS and adaptive routing can potentially improve the NoC efficiency. We further notice that GPU traffic can sometimes tolerate a slack defined as the number of cycles a packet can be delayed without causing performance penalty. In this work, we take advantage of the slack in GPU packets to route packets through non-minimal path, so that routers can operate at a lower frequency without suffering performance penalty.

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A variable frequency link for a power-aware network-on-chip (NoC)

Cited by 47 publications

References 17 publications

Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs

Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs

Power-aware Manhattan Routing on Chip Multiprocessors

Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems

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