In this paper, we revisit traditional checkpointing and rollback recovery strategies, with a focus on silent data corruption errors. Contrarily to fail-stop failures, such latent errors cannot be detected immediately, and a mechanism to detect them must be provided. We consider two models: (i) errors are detected after some delays following a probability distribution (typically, an Exponential distribution); (ii) errors are detected through some verification mechanism. In both cases, we compute the optimal period in order to minimize the waste, i.e., the fraction of time where nodes do not perform useful computations. In practice, only a fixed number of checkpoints can be kept in memory, and the first model may lead to an irrecoverable failure. In this case, we compute the minimum period required for an acceptable risk. For the second model, there is no risk of irrecoverable failure, owing to the verification mechanism, but the corresponding overhead is included in the waste. Finally, both models are instantiated using realistic scenarios and application/architecture parameters.

International audienceA significant percentage of the computing capacity of large-scale platforms is wasted because of interferences incurred by multiple applications that access a shared parallel file system concurrently. One solution to handling I/O bursts in large-scale HPC systems is to absorb them at an intermediate storage layer consisting of burst buffers. However, our analysis of the Argonne's Mira system shows that burst buffers cannot prevent congestion at all times. Consequently, I/O performance is dramatically degraded, showing in some cases a decrease in I/O throughput of 67%. In this paper, we analyze the effects of interference on application I/O bandwidth and propose several scheduling techniques to mitigate congestion. We show through extensive experiments that our global I/O scheduler is able to reduce the effects of congestion, even on systems where burst buffers are used, and can increase the overall system throughput up to 56%. We also show that it outperforms current Mira I/O schedulers

Sustained-release fampridine (fampridine-SR) improves gait velocity and self-perceived capacities in people with multiple sclerosis (MS). However, little is known about the treatment's effect on temporospatial gait parameters, walking endurance, general fatigue, hand function and quality of life (QoL). We therefore sought to evaluate these parameters in a real-world setting: 120 consecutive, eligible patients with MS were evaluated at baseline (D0) and after two weeks (D14) of fampridine-SR. Lastly, D14 responders were again evaluated after three months (M3). Response to treatment was defined as a 15% improvement in at least one of the following tests: the Timed 25-Foot-Walk (T25FW), the 2-min walk test (2MWT) and the Multiple Sclerosis Walking Scale (MSWS-12). Eighty-three patients (74%) were found to be responders. The response rate was lower when assessed as a 20% improvement in the T25FW (50.9%), and this difference was particularly marked for fast-walking subjects (i.e. T25FW <8 s at baseline). Responders displayed mean improvements (at D14 and M3, respectively) of 34.5 and 35.5% in the T25FW, 39 and 36.7% in the 2MWT and 19 and 11.6% in the MSWS-12. The increase in gait velocity was due to both a higher cadence and a greater step length. Responders showed also significant, lasting reductions in fatigue (visual analogue scale and the Fatigue Severity Scale; p < 10(-4) at D14 and <0.01 at M3) and significant, lasting improvements in hand function (9 Hole Peg Test; p < 0.05) and QoL (SF-12; p < 0.01). In conclusion, several MS-induced symptoms other than gait velocity may be improved by fampridine-SR, even if this remains to be more specifically evaluated in future studies.

Résumé : L'ordonnancement d'applications sur des plates-formes parallèles est un problème difficile, et ce d'autant plus si ces plates-formes sont hétérogènes. Une approche de haut niveaù a la programmation parallèle,à base de squelettes algorithmiques, permet toutà la fois de faciliter la tâche du développeur, et d'acquérir des informations structurelles supplémentaires sur l'application, qui permettront d'obtenir un meilleur résultat.Dans ce rapport, on discute l'ordonnancement d'applications sous forme du squelette pipeline sur différent types de plates-formes: les plates-formes totalement homogènes (processeurs et liens de communication identiques), les plates-formesà communications homogènes mais avec des vitesses de processeurs différentes, et les plates-formes totalement hétérogènes. On suppose qu'uné etape de pipeline doitêtre placée sur un unique processeur, et onétablit de nouveaux résultats de complexité pour différentes stratégies d'allocation: on peut imposer qu'au plus uneétape de pipeline soit allouéeà chaque processeur, ou bien allouer un intervalle d'étapes consécutives aux processeurs. Une troisième politique ne fixe aucune contrainte d'allocation.Nous donnons de nombreuses heuristiques polynomiales efficaces pour la combinaison stratégie/plateforme la plus importante,à savoir le placement par intervalle sur plates-formesà communications homogènes. Ces heuristiques sont comparées au résultat optimal obtenu par une formulation du problème sous forme de programme linéaire, pour de petites instances du problème.