An adaptive mesh refinement strategy of substrate modeling for smart power ICs

Zeng, Hao; Moursy, Yasser; Iskander, Ramy; Chaput, Jean-Paul; Louërat, Marie-Minerve

doi:10.1109/iscas.2016.7539058

Cited by 2 publications

(2 citation statements)

References 5 publications

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“…This reduction is essential to simplify the extracted netlist meanwhile keeping the most relevant information for the parasitic coupling analysis [10]. An adaptive meshing strategy is used to reduce the number of the components [11]. The meshing in the vertical direction can significantly affect the results as shown in [12], [13].…”

Section: Automics: Pragmatic Substrate Parasitic Extraction Framementioning

confidence: 99%

Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications

Moursy

Zeng

Khalil

et al. 2017

IEEE Trans. Power Electron.

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Abstract-This paper presents a methodology to analyze the substrate noise coupling and reduce their effects in smart power integrated circuits. This methodology considers the propagation of minority carriers in the substrate. Hence, it models the lateral bipolar junction transistors that are layout dependent and are not modeled in conventional substrate extraction tools. It allows the designer to simulate substrate currents and check their effects on circuits functionality. The proposed methodology employs a dedicated tool for substrate network generation referred to as AUTOMICS. We applied the methodology on two test cases. The first case is a DC-DC buck converter chip fabricated with a 0.35 µm HV-CMOS technology. The DC coupling current between the switches and the bandgap circuit is simulated and verified with measurements. The second test case is an automotive industrial chip that has a latch-up failure due to substrate coupling. In transient simulations, the failure has been reproduced as in measurements. This highlights the stronghold of the methodology since it can be used to prevent this type of failures before fabrication. The proposed methodology can reduce the number of redesigns in the automotive industry. Hence, it shortens the time-to-market, improves the robustness of the design, and reduces the cost.

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Section: Automics: Pragmatic Substrate Parasitic Extraction Framementioning

confidence: 99%

Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications

Moursy

Zeng

Khalil

et al. 2017

IEEE Trans. Power Electron.

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“…This method relies on a rectilinear mesh in 2-D where substrate region is modeled. In [18], an enhanced strategy for 2-D surface meshing was introduced, which contribute to reduce significantly the size of meshing, thus speed up the entire simulation time. In this section, we recall this mesh refinement strategy on the "top" slice of structure, thus the idea can be applied to each one of the entire meshing in 3-D.…”

Section: ) 2-d Surface Meshingmentioning

confidence: 99%

Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology

Zeng

Moursy

Iskander

et al. 2016

IEEE Trans. Circuits Syst. I

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Smart Power integrated circuits receive an increasing attraction recently, especially in automotive industry. Substrate noise coupling is one of the major causes of failure in this kind of integrated circuits that requires circuit redesign and increases the overall cost. An exhaustive failure analysis is needed to identify failures due to substrate coupling. In this paper, we present a post-layout extraction and simulation methodology for substrate parasitic modeling. Based on this methodology, we have developed a dedicated Computer-Aided-Design tool that is used for substrate extraction from layout patterns. The extraction employs a meshing algorithm for substrate parasitic generation.To validate the substrate model, the process of benchmarking uses industrial design structures in 0.35µm high-voltage-CMOS technology. Two test cases in transient simulation are considered in this work. The first one is a common used current mirror circuit. Our tool predicts the interference of substrate currents to this basic circuit. The second test case is an industrial design test-chip where parasitic coupling is investigated in a standard automotive test. Eventually, by using the proposed CAD tool, it becomes possible to simulate the behaviors of substrate noise at early phase before fabrication.

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An adaptive mesh refinement strategy of substrate modeling for smart power ICs

Cited by 2 publications

References 5 publications

Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications

Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications

Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology

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