This paper presents background offset and gain calibration for time-interleaved analog-to-digital converter (TIADC). The calibration technique depends on detecting the offset and the amplitude of a calibration signal. The detection is based on a simple algorithm performed in the digital part. A digital sinusoidal wave is needed to implement the calibration technique. The calibration technique behaviors are theoretically analysed and verified by simulations. A 12-bit, 4-channel, 800 MS/s TIADC is used as an example.

This paper presents a background time skew calibration technique for time-interleaved analog-to-digital converter (TIADC). It depends on the phase detection between a digitally generated calibration signal and the output of each ADC in the system that suffers from time skew mismatch. Digitally controlled delay lines (DCDL) are used to minimize the time skew mismatches among the clock routes. The calibration technique behaviors are theoretically analysed and verified by simulations. A 12-bit 4-channel, 800 MS/s TIADC is used as an example.

This paper proposes a fully-integrated solution for the PI compensation circuits in current-mode DC-DC converters used in automotive applications. In such applications, the switching frequencies are low and hence conventional PI compensation circuits employ large capacitors. The proposed analog/mixedsignal PI comprises an analog proportional amplifier and a digital integrator. The analog proportional amplifier provides the required response time and maintains system stability. The digital integrator block is used to eliminate the output voltage steady-state error. Simulink is used to model the proposed DC-DC buck converter on the system level. The proposed system is verified by full system level simulation. The digital part is synthesized with HDL coder and laid-out using 0.35 µm CMOS technology. The estimated silicon area of the proposed solution is about 0.1 mm 2 . This result highlights the simplicity and the capacity for integration of the proposed control loop along with its potential for seamless implementation into pre-existing solutions with minor modifications.

This paper presents a functional design and modeling of a successive approximation analog-to-digital converter (ADC) and its application in the conditioning circuit of the vibration energy harvester. The paper published on BMAS'09 highlighted the necessity of a smart digital control to calibrate the system, which requires in turn an ultra low power supplied ADC. The harvester and the ADC are designed using a CMOS 0.35µm High Voltage technology and modeled in a mixed VHDL-AMS/ELDO environment. The supply voltage of the ADC is 2.5V. The whole system was simulated using a mixed signal AdvanceMS simulator.