This paper presents background offset and gain calibration for time-interleaved analog-to-digital converter (TIADC). The calibration technique depends on detecting the offset and the amplitude of a calibration signal. The detection is based on a simple algorithm performed in the digital part. A digital sinusoidal wave is needed to implement the calibration technique. The calibration technique behaviors are theoretically analysed and verified by simulations. A 12-bit, 4-channel, 800 MS/s TIADC is used as an example.

This paper presents a background time skew calibration technique for time-interleaved analog-to-digital converter (TIADC). It depends on the phase detection between a digitally generated calibration signal and the output of each ADC in the system that suffers from time skew mismatch. Digitally controlled delay lines (DCDL) are used to minimize the time skew mismatches among the clock routes. The calibration technique behaviors are theoretically analysed and verified by simulations. A 12-bit 4-channel, 800 MS/s TIADC is used as an example.

International audienceA bottom plate sampling switch sharing technique is proposed to enable split ADC calibration with high frequency inputs for Sample and Hold Amplifier-less (SHA-less) pipeline ADCs. The shared bottom plate switch ensures that both halves of the ADC sample the input at the same time, which restores the calibration accuracy for fast varying inputs without the presence of a front-end SHA, thereby significantly reducing area and power consumption. For further power reduction, a feedforward two stage amplifier has been used to push the speed of the amplifier at lower current consumption and low supply voltage. A 12-bit 200 MS/s pipeline ADC has been designed in 40 nm CMOS technology, and the transistor level simulations of the ADC prove the efficiency of the proposed technique to restore the split ADC calibration accuracy in SHA-less pipeline ADCs

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