An adaptive pam-4 5-Gb/s backplane transceiver in 0.25-μm CMOS

Stonick, J.T.; Wei, Gu-Yeon; Sonntag, J.; Weinlader, D.

doi:10.1109/jssc.2002.808282

Cited by 118 publications

(54 citation statements)

References 3 publications

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“…At high frequencies, the resistance of the wire increases and is accompanied by an effective internal inductance. The skin loss can be expressed as (1) where is the wire length, is the permeability, and is the conductivity. Interestingly, the phase shift and amplitude attenuation are identical for skin effect.…”

Section: Amplitude Pre-emphasismentioning

confidence: 99%

“…Since the transmitter operates from a fixed voltage supply, a maximum peak power limits the swing of the higher levels. One-tap amplitude pre-emphasis tends to provide some compensation for the frequency-dependent losses, however, more robust approaches use multiple taps to implement the transmit finite-impulse response (FIR) filter at the expense of additional power consumption [1], [2], [13].…”

Section: Amplitude Pre-emphasismentioning

confidence: 99%

“…Pre-emphasis-based equalization in the transmitter and decision feedback equalization in the receiver figure prominently in overcoming signal degradation and improving the bit-error rate (BER) [1]- [3]. Currently, one challenge of equalization is minimizing power consumption while still improving signal integrity in the presence of attenuation and reflections.…”

mentioning

confidence: 99%

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Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Buckwalter

Meghelli

Friedman

et al. 2006

IEEE J. Solid-State Circuits

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Abstract-A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase preemphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6 Gb/s and 600 mVpp output swing, a power budget of 3 mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24 mW, a budget of 4 mW/Gb/s.

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Section: Amplitude Pre-emphasismentioning

confidence: 99%

Section: Amplitude Pre-emphasismentioning

confidence: 99%

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Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Buckwalter

Meghelli

Friedman

et al. 2006

IEEE J. Solid-State Circuits

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“…[nm] need for a Digital-to-Analog Converter (DAC) at the transmitters, an Analog-to-Digital Converter (ADC) at the receiver, and complex clock recovery schemes [17][18][19][20][21][22][23][24]. High-order PAM was also used for wireline communications to improve spectral efficiency.…”

Section: Referencesmentioning

confidence: 99%

Design Techniques for High-Speed I/Os: Challenges and Opportunities

Yuan¹

2014

J Elec Electron Syst

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“…Increasingly, the channel behavior must be considered and compensated appropriately to reach the highest information capacity. Significant attention has recently been dedicated toward pushing data rates over legacy FR-4 toward 10 Gb/s [1]- [3]. Noise considerations dictate the choice of equalization technique.…”

Section: Introductionmentioning

confidence: 99%

Analysis and Equalization of Data-Dependent Jitter

Buckwalter

Hajimiri

2006

IEEE J. Solid-State Circuits

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Abstract-Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase-and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10 12 BER from 30 to 52 ps at 10 Gb/s.

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An adaptive pam-4 5-Gb/s backplane transceiver in 0.25-μm CMOS

Cited by 118 publications

References 3 publications

Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Phase and Amplitude Pre-Emphasis Techniques for Low-Power Serial Links

Design Techniques for High-Speed I/Os: Challenges and Opportunities

Analysis and Equalization of Data-Dependent Jitter

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