This paper presents the design of a charge sharing 1 bit DAC with pseudo resistors suitable for an asynchronous level crossing ADC. Dummy NMOS devices are added to the 1 bit DAC for reducing the charge accumulation and clock feed through giving a 81.26 % increase in SFDR for 5 kHz input frequency compared to the 1 bit DAC with only pseudo resistors. The asynchronous control logic for the DAC is designed digitally and optimized for lower power consumption. The DAC and its control logic has been designed using 180nm technology in cadence using a supply voltage of 0.8 V and consumes an average power of 2.323 nW.
Keyword: Digital to Analog Converters (DAC), Analog to Digital Converters (ADC), Asynchronous, Level crossing, pseudo resistors
I. INTRODUCTIONAsynchronous ADC architectures are emerging as an excellent alternative for replacing synchronous ADCs in various applications such as portable and implantable biomedical signal sensing devices, remote environmental monitors and sensors, military applications, magnetic disk reader, optical disk readers and wireless applications such as audio devices and cellular telephones. The advantages of asynchronous circuits compared to their synchronous counter parts are higher speed, lower power consumption, and smaller area, immunity to metastable behaviour, less clock skew and low susceptibility to electromagnetic interference. Level crossings ADCs are asynchronous ADCs that generate output samples only when the input signal crosses a threshold level [1]. Level crossing ADCs offers lower sampling rate, power consumption and area than synchronous ADCs. Level crossing ADC has been mainly used in embedded sensing systems, such as environmental sensors (temperature, pressure sensors), implantable biomedical applications, hearing aids and ultrasound applications [2]- [7], [10],[ 11]. This paper presents the design of a charge sharing 1 bit DAC with pseudo resistors and additional dummy NMOS devices for a level crossing ADC. A digital DAC logic using gates and latches for the control of the 1 bit DAC asynchronously is also designed in this paper. In this paper, section II discusses previous literatures on DAC used in level crossing ADCs. Section III gives the circuit implementation followed by results and discussion in section IV. Section V gives the conclusion of the paper.