An Adaptive Thermal Management Framework for Heterogeneous Multi-Core Processors

Kim, Young Geun; Kim, Minyong; Kong, Joonho; Chung, Sung Woo

doi:10.1109/tc.2020.2970062

Cited by 26 publications

(22 citation statements)

References 43 publications

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“…Figure 5 shows the normalized energy efficiency (PPW) and latency of DNN (i.e., MobilenetV3) inference when CPUintensive or memory-intensive synthetic applications are corunning, changing the optimal execution target. When a CPUintensive application is co-running, the energy efficiency of the inference execution on CPU is significantly degraded, due to 1) competitions for CPU resources, and 2) frequent thermal throttling from high CPU utilization [50]. In this case, the optimal execution target shifts from the CPU to the GPU.…”

Section: Impact Of Runtime Variance On Inference Executionmentioning

confidence: 99%

AutoScale: Optimizing Energy Efficiency of End-to-End Edge Inference under Stochastic Variance

Kim,

2020

Preprint

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Deep learning inference is increasingly run at the edge. As the programming and system stack support becomes mature, it enables acceleration opportunities within a mobile system, where the system performance envelope is scaled up with a plethora of programmable co-processors. Thus, intelligent services designed for mobile users can choose between running inference on the CPU or any of the co-processors on the mobile system, or exploiting connected systems, such as the cloud or a nearby, locally connected system. By doing so, the services can scale out the performance and increase the energy efficiency of edge mobile systems. This gives rise to a new challenge-deciding when inference should run where. Such execution scaling decision becomes more complicated with the stochastic nature of mobile-cloud execution, where signal strength variations of the wireless networks and resource interference can significantly affect real-time inference performance and system energy efficiency. To enable accurate, energy-efficient deep learning inference at the edge, this paper proposes AutoScale. AutoScale is an adaptive and light-weight execution scaling engine built upon the customdesigned reinforcement learning algorithm. It continuously learns and selects the most energy-efficient inference execution target by taking into account characteristics of neural networks and available systems in the collaborative cloudedge execution environment while adapting to the stochastic runtime variance. Real system implementation and evaluation, considering realistic execution scenarios, demonstrate an average of 9.8 and 1.6 times energy efficiency improvement for DNN edge inference over the baseline mobile CPU and cloud offloading, while meeting the real-time performance and accuracy requirement.

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Section: Impact Of Runtime Variance On Inference Executionmentioning

confidence: 99%

AutoScale: Optimizing Energy Efficiency of End-to-End Edge Inference under Stochastic Variance

Kim,

2020

Preprint

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“…The overheating of the chip reduces the integrated circuit performance, shortens the lifetime of the chip, and even leads to chip failure [1,2]. To solve the thermal problem, the dynamic thermal management (DTM) technique has been proposed [3][4][5][6]. DTM can effectively inhibit the occurrence of chip overheating by analysing the real-time thermal field information on the whole chip and taking proper actions to control the temperature within an appropriate temperature range.…”

Section: Introductionmentioning

confidence: 99%

“…DTM can effectively inhibit the occurrence of chip overheating by analysing the real-time thermal field information on the whole chip and taking proper actions to control the temperature within an appropriate temperature range. When the temperature exceeds a given temperature triggering threshold, management procedures are started and reasonable actions, such as appropriately regulating frequencies and voltages, are taken to bring the temperature back within the acceptable range [5,6].…”

Section: Introductionmentioning

confidence: 99%

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Thermal field reconstruction based on weighted dictionary learning

Zhang

Xiao³

et al. 2021

IET Circuits, Devices & Syst

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Dynamic thermal management (DTM) is applied to address the thermal problem of high performance very-large-scale integrated chips. The false alarm rate (FAR) can be used to evaluate the impact of full-chip thermal field reconstruction accuracy on DTM. A low FAR relies on the accurate reconstruction of the full thermal field, especially near the temperature triggering threshold of DTM. However, little attention is currently being paid to such temperature ranges. To reduce FAR, a new full-chip thermal field reconstruction strategy is proposed. A low-dimensional linear model is used to accurately represent the thermal fields. The dictionary learning technology is exploited to train the model and the minimum weighted mean square error evaluation method is incorporated to improve the reconstruction accuracy near the temperature triggering threshold. A temperature sensor placement algorithm using the heuristic algorithm to solve the NPhard problem is also proposed. The experimental results show that the proposed strategy can reconstruct the full thermal field with a more precise accuracy near the triggering threshold and achieve the lowest FAR compared to the state of the art.

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“…In addition, we implemented the Popcount unit with Verilog HDL. Then, we synthesized and placed-and-routed the Popcount unit with the Synopsys Design Compiler [12] and IC Compiler [13]. We exploited the Samsung System LSI 28 nm ASIC library.…”

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confidence: 99%

A System-Level Exploration of Binary Neural Network Accelerators with Monolithic 3D Based Compute-in-Memory SRAM

2021

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Binary neural networks (BNNs) are adequate for energy-constrained embedded systems thanks to binarized parameters. Several researchers have proposed the compute-in-memory (CiM) SRAMs for XNOR-and-accumulation computations (XACs) in BNNs by adding additional transistors to the conventional 6T SRAM, which reduce the latency and energy of the data movements. However, due to the additional transistors, the CiM SRAMs suffer from larger area and longer wires than the conventional 6T SRAMs. Meanwhile, monolithic 3D (M3D) integration enables fine-grained 3D integration, reducing the 2D wire length in small functional units. In this paper, we propose a BNN accelerator (BNN_Accel), composed of a 9T CiM SRAM (CiM_SRAM), input buffer, and global periphery logic, to execute the computations in the binarized convolution layers of BNNs. We also propose CiM_SRAM with the subarray-level M3D integration (as well as the transistor-level M3D integration), which reduces the wire latency and energy compared to the 2D planar CiM_SRAM. Across the binarized convolution layers, our simulation results show that BNN_Accel with the 4-layer CiM_SRAM reduces the average execution time and energy by 39.9% and 23.2%, respectively, compared to BNN_Accel with the 2D planar CiM_SRAM.

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An Adaptive Thermal Management Framework for Heterogeneous Multi-Core Processors

Cited by 26 publications

References 43 publications

AutoScale: Optimizing Energy Efficiency of End-to-End Edge Inference under Stochastic Variance

AutoScale: Optimizing Energy Efficiency of End-to-End Edge Inference under Stochastic Variance

Thermal field reconstruction based on weighted dictionary learning

A System-Level Exploration of Binary Neural Network Accelerators with Monolithic 3D Based Compute-in-Memory SRAM

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