An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers

Hwang, Sun Jin; Song, Junyoung; Bae, Sang-Geun; Lee, Yeonho; Kim, Chulwoo

doi:10.1109/tvlsi.2015.2435026

Cited by 2 publications

(2 citation statements)

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“…As the data rate increases, the received data are more affected by high-frequency jitter. Several techniques have been proposed to enhance jitter tolerance [14]- [16]. However, jitter tolerance enhancement using a gate-digital-controlledoscillator (GDCO) requires an additional circuit for the GDCO frequency preset [14].…”

Section: Introductionmentioning

confidence: 99%

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A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector

Choi

Hwang²,

Lee

et al. 2021

IEEE Access

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This paper presents an area-and energy-efficient digital sub-sampling clock and data recovery (CDR) with combined adaptive equalizer and self-error corrector (SEC). Using the digitized phase difference between the incoming data and the full-rate output clock of a digitally controlled oscillator (DCO) for both the equalizer adaptation and clock recovery loop, the proposed adaptive equalizer is combined with the CDR by sharing its adaptation loop including a sub-sampling phase detector (SSPD) and a digital logic circuit. Consequently, the active area and power dissipation for the adaptive equalizer are reduced. Furthermore, the SEC is proposed to improve the high-frequency jitter tolerance of the CDR. The SEC detects bit errors by observing the comparator decision and corrects the errors without any data encoding or complicate circuits. The out-of-band jitter tolerance is improved by 22.6% at 100 MHz for 17.2-dB loss channel with <10 -12 biterror rate (BER) with the proposed SEC. The SEC is applicable to various receivers with compact design at a low cost. The prototype receiver consumes 23.9 mW at 14-Gb/s and occupies 0.007 mm 2 in a 28-nm CMOS technology.INDEX TERMS Adaptive equalizer, clock and data recovery (CDR), continuous-time linear equalizer (CTLE), decision feedback equalizer (DFE), jitter tolerance, receiver, self-error corrector (SEC), subsampling.

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Section: Introductionmentioning

confidence: 99%

“…In addition, increasing the jitter tracking bandwidth increases the unwanted clock jitter [15]. A real-time phase alignment scheme without increasing the CDR bandwidth is proposed in [16]. However, it necessitates complicate circuits that require large power and area.…”

Section: Introductionmentioning

confidence: 99%